# How to use SiFive Core IP FPGA Eval Kit for different FPGAs? **URL:** \ **Category:** General\ **Created:** [April 3, 2019, 5:18pm UTC](https://forums.sifive.com/t/how-to-use-sifive-core-ip-fpga-eval-kit-for-different-fpgas/2188 "2019-04-03T17:18:18Z")\ **Posts on this page:** 2\ **Page:** 1
**Author:** ![hyf6661669](https://avatars.discourse-cdn.com/v4/letter/h/43a26b/32.png) [@hyf6661669](https://forums.sifive.com/u/hyf6661669)\ **Post date:** [April 3, 2019, 5:18pm UTC](https://forums.sifive.com/t/how-to-use-sifive-core-ip-fpga-eval-kit-for-different-fpgas/2188/1 "2019-04-03T17:18:18Z")
I have downloaded some interesting Core IP FPGA Eval Kits in [https://www.sifive.com/core-designer](https://www.sifive.com/core-designer), but I find that the prebuilt .mcs file is generated for Arty\_100T. For example, the name of the .mcs file in sifive\_coreip\_E34\_eval\_dev\_kit\_v1p0\fpga is sifive\_coreip\_E34\_FPGA\_Evaluation\_Arty\_100T\_v1p0\_rc0.mcs. Unfortunately, I don’t have a Arty board from Digilent or Avent. I’m using a Genesys2 boad with xc7k325t. But I still want to try out your cores on my FPGA. I find that there are some verilog source files in “verilog/design” and “verilog/memories”, which seem could be used in Vivado or Quartus. I have already tried out the " Freedom E300 Arty FPGA Dev Kit" from [https://github.com/sifive/freedom](https://github.com/sifive/freedom), but I still want to evaluate more cores. So is it possible for me to use these verilog files to generate a useable bitstream file for my FPGA? Could you write some guides on how to put the FPGA Eval Kits into different FPGA? Much thanks!! ---
**Author:** ![hyf6661669](https://avatars.discourse-cdn.com/v4/letter/h/43a26b/32.png) [@hyf6661669](https://forums.sifive.com/u/hyf6661669)\ **Post date:** [April 12, 2019, 12:57am UTC](https://forums.sifive.com/t/how-to-use-sifive-core-ip-fpga-eval-kit-for-different-fpgas/2188/2 "2019-04-12T00:57:02Z")
Can anyone give some useful information ?