How to upload peograms to Arty 7 and debug by jtag interference?


(Donnie Agema) #16

I have used the Olimex debugger using bioth freedom-e-sdk and FreedomStudio, on Corplex IP only. I have not yet been able to get my own Chisel generated bitstream to work.


(pengnainqi) #17

Thanks Donnie,

You operating system is linux ? I always debug failed. The Olimex debugger need installing driver in windows ? The wire between debugger and computer is okay.


(Donnie Agema) #18

I have successfully used the Olimex debugger on a Linux virtual machine running on a Windows 7 machine, on the Windows 7 machine directly using the FreedomStudio for Windows, and also on Windows 7 running Cygwin (see this thread).

On Linux, is your Olimex appearing in the devices list as described in chapter 4 of the getting started guide?


(Megan A. Wachs) #19

Hi @pengnainqi,

Can you tell me the difference between Coreplex IP and Freedom E300 Dev Kit ? If you try debug with "ARM-USB-TINY-H" ? Thanks agin !

Donnie is right. Just to add some more detail, you can think of the Freedom E300 Dev Kit (downloaded from here: https://dev.sifive.com/freedom-soc/evaluate/fpga/) as an FPGA version of the FE310 chip. As such, it is using a slightly older version of the Debug protocol, and has a different JTAG IDCODE, and has peripherals and pinout to match the FE310. All this is handled automatically when you say BOARD=freedom-e300-arty. And if you build your own MCS file from the Freedom repository (github.com/sifive/freedom), you should use the same BOARD argument.

The E31 Coreplex IP FPGA Dev Kit (downloaded from here: https://dev.sifive.com/coreplex-risc-v-ip/evaluate/fpga/) uses a newer version of the Debug protocol, has a different JTAG IDCODE, and has different peripherals. Which is why you should use BOARD=coreplexip-e31-arty (or e51) when using those MCS files.


(pengnainqi) #20

Thanks mwach,

Your explanation deepen my understanding of the difference between coreplexip e31 and freedom e300 dev kit. So,I have another question. I have generated Verilog code in the directory of freedom (www.github.com/sifive/freedom ) is coreplex ip or freedom e300 dev kit ?How to ge FPGA bitstream file not contain demo program?


(pengnainqi) #21

Thanks Donnie very much,

Your advice every time always help me a lot ! my Olimex appearing in the devices list as described in chapter 4 of the getting started guide, but debug always failed ! Thanks again !


(Donnie Agema) #22

Hmm. . . have you tried poweríng the Arty from its 12V barrel connector instead of the USB connector?


(pengnainqi) #23

The wire between debugger and arty is okay, but errors always not change. I want to cry.:sob:


(Donnie Agema) #24

Sorry, but short of suspecting an electrical defect in either the Olimix or the Arty, I am running out of suggestions. Please double-check that JP1 and JP2 on the Arty are shorted, and that you have connected the Olimex to the JD connector (next to the RESET pushbutton).

Also, you might try removing and re-installing the Olimex driver.


(pengnainqi) #25

Thanks Donnie,

Not work!:joy:


(Donnie Agema) #26

I can see on your PM screenshot that you have successfully initiated a debug session under windows, so your hardware and wiring must be functioning correctly. Since your Linux environmnt appears to be unable to find the Olimex, I am wondering if you have correctly set the group access privilege for the Olimex.


(pengnainqi) #28

Hi Donnie,

Maybe look likes better!



(pengnainqi) #29

But i dont know how to solve.


(Donnie Agema) #30

I have invidted help from the SiFive experts to help you solve ít, now that your debug connection is working.


(pengnainqi) #31

okay,thanks !


(Megan A. Wachs) #32

There is no error, the “Error” is an expected one (the debugger causes it as part of deciding whether the core is 32-bit or 64-bit).

Your board is ready to accept connections from GDB.

So now in another window you can do “make run_gdb BOARD=… PROGRAM=…” and start debugging.

Or if you just want to upload your code, you can just do “make upload …”


(pengnainqi) #33

Wow,Thanks very much!

I want to know that the command of "make upload… " will show the program result to host screen ? :blush:


(pengnainqi) #34

Hi mwach,

  1. “make upload PROGRAM=dhrystone BOARD=coreplexip-e31-arty”



Two questions,

(1) The error “unable to execute program” don’t effect running debug? why not program output when uploading
to the board?

(2) Why cpu state is “halted”?

2 .“make run_gdb BOARD=coreplexip-e31-arty”



Why connection timed out???


(pengnainqi) #36

Thanks,

This is the result of running gdb in windows environment !



Why always stay 99%?


(tang chuan) #37

I have the same problem with you, but i use zcu102 to Implement hybird (risc-v core). How did you solve that can’t find Jtag???thaks, pengnainqi