# How to deal with local interrupts in HiFive1? **URL:** \ **Category:** HiFive1 Rev B\ **Created:** [July 8, 2017, 3:06pm UTC](https://forums.sifive.com/t/how-to-deal-with-local-interrupts-in-hifive1/632 "2017-07-08T15:06:29Z")\ **Posts on this page:** 8\ **Page:** 1
**Author:** ![embden](https://avatars.discourse-cdn.com/v4/letter/e/e5b9ba/32.png) [@embden](https://forums.sifive.com/u/embden)\ **Post date:** [July 8, 2017, 3:06pm UTC](https://forums.sifive.com/t/how-to-deal-with-local-interrupts-in-hifive1/632/1 "2017-07-08T15:06:29Z")
Hello, I am trying to handle local interrupts. That’s what I do, in my handler for timer interrupts: - disable timer interrupts in mie - read a current value from mtime - copy it to mtimecmp (both are 64bit width types) - add some big value to mtimecmp - enable timer interrupts in mie. And I have two boards and the problem is that on one of them interrupts are permanently generated because mip register is always 1 in mtip position, though mtimecmp is greater than mtime, and are not generated at all on the other. In this piece of code, I turn on interrupts: la t0, RISCV\_Exception\_default csrs mtvec, t0 li t0, 0x88 csrs mie, t0 csrsi mstatus, 0x8 My start file: [start.S](https://github.com/embeddedden/rtems-riscv/blob/hifive1/c/src/lib/libbsp/riscv32/hifive1/start/start.S) and ISR: [irq.c](https://github.com/embeddedden/rtems-riscv/blob/hifive1/c/src/lib/libbsp/riscv32/hifive1/irq/irq.c) ---
**Author:** ![embden](https://avatars.discourse-cdn.com/v4/letter/e/e5b9ba/32.png) [@embden](https://forums.sifive.com/u/embden)\ **Post date:** [July 8, 2017, 6:42pm UTC](https://forums.sifive.com/t/how-to-deal-with-local-interrupts-in-hifive1/632/2 "2017-07-08T18:42:48Z")
Now my boards behave in the same way - I can’t clear interrupt pending bit in mtip, so interrupts keep generating. ---
**Author:** ![mwachs5](https://sea2.discourse-cdn.com/flex020/user_avatar/forums.sifive.com/mwachs5/32/13_2.png) [@mwachs5](https://forums.sifive.com/u/mwachs5)\ **Post date:** [July 8, 2017, 10:11pm UTC](https://forums.sifive.com/t/how-to-deal-with-local-interrupts-in-hifive1/632/3 "2017-07-08T22:11:36Z")
MTIME and MTIMECMP are 64-bit values, as you mentioned above. But in your start.S, you seem to be treating them only as 32-bit values. MTIMECMP is not reset to 0, so you should, at least, set the upper bits of MTIMECMP as well. The RISC-V Privileged Spec has a snippet for how to safely set MTIMECMP on a 32-bit system. In your irq.c you are treating them as 64-bit values, but I’m wondering if you are ever even getting that far since the first MTIMECMP may be wrong. Another note, you probably want to use csrw, not csrs, to set mtvec. ---
**Author:** ![embden](https://avatars.discourse-cdn.com/v4/letter/e/e5b9ba/32.png) [@embden](https://forums.sifive.com/u/embden)\ **Post date:** [July 8, 2017, 10:52pm UTC](https://forums.sifive.com/t/how-to-deal-with-local-interrupts-in-hifive1/632/4 "2017-07-08T22:52:31Z")
Thank you, yes, in my start.S it is only 32-bit value as a quick solution, because my counter never overflows 32-bit value(never runs so long). I will change it a bit later. In my irq.c there is also a temporary static variable cntr, which is incremented at the handler. And after some time running I can see a big value in cntr. Also, there is a static array Times, and now for example, I can run my executable and print the values. These are first 10 values if mtime during interrupts’ triggering: (gdb) p /x \*times@10 $66 = {0x63650, 0x63669, 0x6366a, 0x6366a, 0x6366a, 0x6366b, 0x6366b, 0x6366c, 0x6366c, 0x6366d} Yes, you are right about csrw. ---
**Author:** ![embden](https://avatars.discourse-cdn.com/v4/letter/e/e5b9ba/32.png) [@embden](https://forums.sifive.com/u/embden)\ **Post date:** [July 9, 2017, 12:31am UTC](https://forums.sifive.com/t/how-to-deal-with-local-interrupts-in-hifive1/632/5 "2017-07-09T00:31:19Z")
I found the problem, I made a mistake in my code, instead of: if ((cause & MCAUSE\_MTIME) == MCAUSE\_MTIME) { I have written: if (cause & MCAUSE\_MTIME) { now local interrupts work. ---
**Author:** ![mwachs5](https://sea2.discourse-cdn.com/flex020/user_avatar/forums.sifive.com/mwachs5/32/13_2.png) [@mwachs5](https://forums.sifive.com/u/mwachs5)\ **Post date:** [July 9, 2017, 6:16pm UTC](https://forums.sifive.com/t/how-to-deal-with-local-interrupts-in-hifive1/632/6 "2017-07-09T18:16:11Z")
Great! I think that line might still be a little off, you may want `if ((cause & MCAUSE_CAUSE) == MCAUSE_MTIME)` to compare the entire cause. EDIT: Corrected thanks to @tommythorn’s feedback below ---
**Author:** ![tommythorn](https://avatars.discourse-cdn.com/v4/letter/t/f0a364/32.png) [@tommythorn](https://forums.sifive.com/u/tommythorn)\ **Post date:** [July 11, 2017, 9:22pm UTC](https://forums.sifive.com/t/how-to-deal-with-local-interrupts-in-hifive1/632/7 "2017-07-11T21:22:59Z")
I assume this was a typo and you really meant ``` if ((cause & MCAUSE_CAUSE) == MCAUSE_MTIME) ``` otherwise it the compiler will treat this is ``` if (cause & (MCAUSE_CAUSE == MCAUSE_MTIME)) ``` thus ``` if (0) ``` ---
**Author:** ![mwachs5](https://sea2.discourse-cdn.com/flex020/user_avatar/forums.sifive.com/mwachs5/32/13_2.png) [@mwachs5](https://forums.sifive.com/u/mwachs5)\ **Post date:** [July 11, 2017, 9:24pm UTC](https://forums.sifive.com/t/how-to-deal-with-local-interrupts-in-hifive1/632/8 "2017-07-11T21:24:23Z")
Yes, thank you. Will edit above