# Help me. I am confused about RISC-V cores
**URL:** https://forums.sifive.com/t/help-me-i-am-confused-about-risc-v-cores/2730
**Category:** General
**Created:** [August 10, 2019, 10:17am UTC](https://forums.sifive.com/t/help-me-i-am-confused-about-risc-v-cores/2730 "2019-08-10T10:17:56Z")
**Posts on this page:** 6
**Page:** 1
### Author:  [@zerox100](https://forums.sifive.com/u/zerox100)
#### Post date: [August 10, 2019, 10:17am UTC](https://forums.sifive.com/t/help-me-i-am-confused-about-risc-v-cores/2730/1 "2019-08-10T10:17:57Z")
Hi
I am PhD student of computer engineering. I am working to build a CGRA accelerator for RISCV. I have done the CGRA accelerator for MIPS32 and ARM7. Now I am switching to RISC-V. I have downloaded lots of RISC-V cores from github and other places. Some of them have bug. Some of them are incomplete. Some of them are written with non HDL languages (VHDL, Verilog). Finally I download S21 and some others from SIFIVE. But this code is not fully RTL. It is something between RTL and netlist and is not readable and understandable codes.
It is my story in these two weeks!!!
Is there any bug free HDL codes for RV32I or RV64I in github or sifive or any other places?
Help me please
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### Author:  [@vmedea](https://forums.sifive.com/u/vmedea)
#### Post date: [August 10, 2019, 3:28pm UTC](https://forums.sifive.com/t/help-me-i-am-confused-about-risc-v-cores/2730/2 "2019-08-10T15:28:50Z")
bug-free is **a lot** to ask, but i expect Clifford Wolf’s [picorv32](https://github.com/cliffordwolf/picorv32) to be as exhaustively formally verified as possible, does RV32I, and it’s verilog …
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### Author:  [@jimw](https://forums.sifive.com/u/jimw)
#### Post date: [August 10, 2019, 4:31pm UTC](https://forums.sifive.com/t/help-me-i-am-confused-about-risc-v-cores/2730/3 "2019-08-10T16:31:48Z")
You can find a list of cores here.
[https://riscv.org/risc-v-cores/](https://riscv.org/risc-v-cores/)
the picorv32 one already mentioned is popular and should work, but is a very small rv32i core.
Since you asked on a SiFive forum, the commercial cores we have available for trial use are obfuscated and unlikely to be useful for development work. We do have two open cores we maintain. Rocket chip which was originally designed at UC Berkeley
[https://github.com/chipsalliance/rocket-chip](https://github.com/chipsalliance/rocket-chip)
and freedom which is rocket chip plus some SiFive designed blocks
[https://github.com/sifive/freedom](https://github.com/sifive/freedom)
Both can be compiled to verilog, and/or compiled to run on an FPGA.
I’m not a hardware guy, so I don’t know the details or how to use either open SiFive core. I would suggest filing issues against the github tree if you have questions about these cores, or any of the other cores.
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### Author:  [@zerox100](https://forums.sifive.com/u/zerox100)
#### Post date: [August 11, 2019, 9:10am UTC](https://forums.sifive.com/t/help-me-i-am-confused-about-risc-v-cores/2730/5 "2019-08-11T09:10:26Z")
> [@zerox100](#):
>
> Thanks for your attention.
> I Have seen this project. But it is not pipelined processor. The picorv32 is mostly designed for clock speed, but its IPC is pretty bad, requiring at least 3 cycles per instructions and often quite a bit more.
Thanks for your attention.
I Have seen this project. But it is not pipelined processor. The picorv32 is mostly designed for clock speed, but its IPC is pretty bad, requiring at least 3 cycles per instructions and often quite a bit more.
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### Author:  [@zerox100](https://forums.sifive.com/u/zerox100)
#### Post date: [August 11, 2019, 3:03pm UTC](https://forums.sifive.com/t/help-me-i-am-confused-about-risc-v-cores/2730/6 "2019-08-11T15:03:13Z")
Thank you mara for your attention.
I Have seen this project. But it is not pipelined processor. The picorv32 is mostly designed for clock speed, but its IPC is pretty bad, requiring at least 3 cycles per instructions and often quite a bit more.
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### Author:  [@thornschuh](https://forums.sifive.com/u/thornschuh)
#### Post date: [August 15, 2019, 8:09am UTC](https://forums.sifive.com/t/help-me-i-am-confused-about-risc-v-cores/2730/7 "2019-08-15T08:09:23Z")
Can you tell me what features you expect from the core?
I’m the author of Bonfire [https://bonfirecpu.eu](https://bonfirecpu.eu)
I can’t say if it is really bug free, most likely not.
But it can successfully run „real world“ code like the Lua scripting language, fatfs or picotcp.
It is my „hobby core“, but I actively maintain it and will try to help with problems.