GPIO pins 6, 7 and 8 missing?

Archive Freedom E300
1

Hi there,

When I am trying to generate verilog using the command make -f Makefile.e300artydevkit verilog, I noticed that the generated verilog does not have GPIO 6, 7 and 8 in platform? Did I do something wrong?

See the verilog here:

input gpio_0_pins_5_i_ival,
output gpio_0_pins_5_o_oval,
output gpio_0_pins_5_o_oe,
output gpio_0_pins_5_o_ie,
input gpio_0_pins_9_i_ival,
output gpio_0_pins_9_o_oval,
output gpio_0_pins_9_o_oe,
output gpio_0_pins_9_o_ie,

Thanks.

2

Since they aren’t connected at the top level, they get constant propagated away in the emitted verilog. If you connect them to something at the top level you will see them again.

3

Thanks @mwachs5, where does it get unconnected in the top level? I didn’t see it in platform.scala? I can see it un-connected in FPGAChip.scala (see https://github.com/sifive/freedom/blob/master/src/main/scala/everywhere/e300artydevkit/FPGAChip.scala#L124)? But that is nothing to do with the platform (https://github.com/sifive/freedom/blob/master/src/main/scala/everywhere/e300artydevkit/Platform.scala) and system (https://github.com/sifive/freedom/blob/master/src/main/scala/everywhere/e300artydevkit/System.scala), right?

4

Right, but the constant propagation is global. Since it is not connected at the top level it is stripped away at Platform and System level in the emitted verilog.

If you want to prevent this behavior, you can use “DontTouch” to prevent it : https://github.com/freechipsproject/rocket-chip/blob/8e1a002c4efab6360861ff0755b4fbd47d623c34/src/main/scala/system/ExampleRocketSystem.scala#L29

5

Thanks @mwachs5!