# GDB (Breakpoint) and OpenOCD problem

**URL:** <https://forums.sifive.com/t/gdb-breakpoint-and-openocd-problem/1384>\
**Category:** Freedom E300\
**Created:** [July 7, 2018, 8:23am UTC](https://forums.sifive.com/t/gdb-breakpoint-and-openocd-problem/1384 "2018-07-07T08:23:25Z")\
**Posts on this page:** 6\
**Page:** 1

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**Author:** ![moonhg1209](https://avatars.discourse-cdn.com/v4/letter/m/35a633/32.png) [@moonhg1209](https://forums.sifive.com/u/moonhg1209)\
**Post date:** [July 7, 2018, 8:23am UTC](https://forums.sifive.com/t/gdb-breakpoint-and-openocd-problem/1384/1 "2018-07-07T08:23:25Z")

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Hello,

I have the Artix-7 35T FPGA and I’m following the freedom platform github.

There was a problem while debugging using openocd and gdb.

**The brakepoint does not work, and the s command also operates abnormally.**

Please help me…

Attach the **make run\_gdb script** below.

**-VirtualBox:~/RISC-V/freedom-e-sdk$ sudo make run\_gdb PROGRAM=demo\_gpio BOARD=freedom-e300-arty**  
/home/moonhg/RISC-V/freedom-e-sdk/work/build/riscv-gnu-toolchain/riscv64-unknown-elf/prefix/bin/riscv64-unknown-elf-gdb software/demo\_gpio/demo\_gpio -ex “set remotetimeout 240” -ex “target extended-remote localhost:3333"  
GNU gdb (GDB) 8.0.50.20170724-git  
Copyright © 2017 Free Software Foundation, Inc.  
License GPLv3+: GNU GPL version 3 or later [http://gnu.org/licenses/gpl.html](http://gnu.org/licenses/gpl.html)  
This is free software: you are free to change and redistribute it.  
There is NO WARRANTY, to the extent permitted by law. Type “show copying"  
and “show warranty” for details.  
This GDB was configured as “–host=x86\_64-pc-linux-gnu --target=riscv64-unknown-elf”.  
Type “show configuration” for configuration details.  
For bug reporting instructions, please see:  
[http://www.gnu.org/software/gdb/bugs/](http://www.gnu.org/software/gdb/bugs/).  
Find the GDB manual and other documentation resources online at:  
[http://www.gnu.org/software/gdb/documentation/](http://www.gnu.org/software/gdb/documentation/).  
For help, type “help”.  
Type “apropos word” to search for commands related to “word”…  
Reading symbols from software/demo\_gpio/demo\_gpio…done.  
Remote debugging using localhost:3333  
0x204000ec in main (argc=, argv=) at demo\_gpio.c:260  
260 atomic\_fetch\_xor\_explicit(&GPIO\_REG(GPIO\_OUTPUT\_VAL), bitbang\_mask, memory\_order\_relaxed);  
**(gdb) monitor reset halt**  
JTAG tap: riscv.cpu tap/device found: 0x20000913 (mfg: 0x489 (SiFive, Inc.), part: 0x0000, ver: 0x2)  
dtmcontrol\_idle=5, dmi\_busy\_delay=5, ac\_busy\_delay=0  
**(gdb) monitor flash protect 0 64 last off**  
cleared protection for sectors 64 through 255 on flash bank 0  
**(gdb) load**  
Loading section .init, size 0x6c lma 0x20400000  
Loading section .text, size 0xbbde lma 0x2040006c  
Loading section .rodata, size 0x1154 lma 0x2040bc50  
Loading section .eh\_frame, size 0x68 lma 0x2040cda4  
Loading section .data, size 0x9d0 lma 0x2040ce0c  
Start address 0x20400000, load size 55254  
Transfer rate: 736 bytes/sec, 6906 bytes/write.  
**(gdb) hb main**  
Hardware assisted breakpoint 1 at 0x2040006c: file demo\_gpio.c, line 197.  
**(gdb) list 210**  
205   
206   
207 int a = 1234;  
208   
209 a = a + 1;  
210   
211 a = a + 10;  
212   
213 printf(”%d”, a);  
214   
**(gdb) hb 209**  
Hardware assisted breakpoint 2 at 0x2040006e: file demo\_gpio.c, line 209.  
**(gdb) c**  
Continuing.

Breakpoint 1, main (argc=0, argv=0x0) at demo\_gpio.c:197  
197 {  
**(gdb) c**  
Continuing.

Breakpoint 2, main (argc=0, argv=0x0) at demo\_gpio.c:213  
213 printf("%d", a);  
**(gdb) s**  
197 {  
**(gdb) s**  
213 printf("%d", a);  
**(gdb) s**  
Note: automatically using hardware breakpoints for read-only addresses.  
Warning:  
Cannot insert hardware breakpoint 0.  
Could not insert hardware breakpoints:  
You may have requested too many hardware breakpoints/watchpoints.

0x20400772 in printf ()  
**(gdb) s**  
Single stepping until exit from function printf,  
which has no line number information.  
keep\_alive() was not invoked in the 1000ms timelimit. GDB alive packet not sent! (1335). Workaround: increase “set remotetimeout” in GDB  
keep\_alive() was not invoked in the 1000ms timelimit. GDB alive packet not sent! (1002). Workaround: increase “set remotetimeout” in GDB  
keep\_alive() was not invoked in the 1000ms timelimit. GDB alive packet not sent! (1002). Workaround: increase “set remotetimeout” in GDB  
keep\_alive() was not invoked in the 1000ms timelimit. GDB alive packet not sent! (1016). Workaround: increase “set remotetimeout” in GDB  
0x204007b2 in \_vfprintf\_r ()  
**(gdb) quit**

and below are **make\_openocd error messages**

Error: Couldn’t find an available hardware trigger.  
Error: can’t add breakpoint: resource not available

How to solve this problem?

Thank you!

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**Author:** ![thornschuh](https://sea2.discourse-cdn.com/flex020/user_avatar/forums.sifive.com/thornschuh/32/134_2.png) [@thornschuh](https://forums.sifive.com/u/thornschuh)\
**Post date:** [July 7, 2018, 9:24pm UTC](https://forums.sifive.com/t/gdb-breakpoint-and-openocd-problem/1384/2 "2018-07-07T21:24:43Z")

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The SiFive core only supports two hardware breakpoints. Because the code resides in read-only flash software breakpoints did not work. Single step on source level in gdb requires sometimes two breakpoints, e.g. when stepping over code containing conditional branches. You have set a breakpoint at the beginning of your debug session, this blocks already one hw breakpoint.  
You should disable this breakpoint before single stepping. This can be a bit anoying.

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**Author:** ![ilg](https://sea2.discourse-cdn.com/flex020/user_avatar/forums.sifive.com/ilg/32/871_2.png) [@ilg](https://forums.sifive.com/u/ilg)\
**Post date:** [July 8, 2018, 2:58am UTC](https://forums.sifive.com/t/gdb-breakpoint-and-openocd-problem/1384/3 "2018-07-08T02:58:55Z")

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> [@thornschuh](#):
>
> The SiFive core only supports two hardware breakpoints.

I complained about this long time ago, and, if I remember right, the E31/E51 cores were upgraded to 8 hw breakpoints; or at least this was the plan.

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**Author:** ![eager](https://avatars.discourse-cdn.com/v4/letter/e/c37758/32.png) [@eager](https://forums.sifive.com/u/eager)\
**Post date:** [July 10, 2018, 5:59pm UTC](https://forums.sifive.com/t/gdb-breakpoint-and-openocd-problem/1384/4 "2018-07-10T17:59:13Z")

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The updated E31 FPGA bitstream has 8 breakpoints:  
[https://dev.sifive.com/dashboard/deliverables/sifive\_e31\_fpga\_eval\_kit\_bitstream/releases/v3p0/](https://dev.sifive.com/dashboard/deliverables/sifive_e31_fpga_eval_kit_bitstream/releases/v3p0/)

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**Author:** ![moonhg1209](https://avatars.discourse-cdn.com/v4/letter/m/35a633/32.png) [@moonhg1209](https://forums.sifive.com/u/moonhg1209)\
**Post date:** [July 12, 2018, 2:50am UTC](https://forums.sifive.com/t/gdb-breakpoint-and-openocd-problem/1384/5 "2018-07-12T02:50:57Z")

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Thank you very much everyone!!

It seems that it does not apply to rocket chip sources that can be compiled yet.

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<div class="post-metadata">

**Author:** ![tgm](https://avatars.discourse-cdn.com/v4/letter/t/c68b51/32.png) [@tgm](https://forums.sifive.com/u/tgm)\
**Post date:** [July 13, 2018, 12:27pm UTC](https://forums.sifive.com/t/gdb-breakpoint-and-openocd-problem/1384/6 "2018-07-13T12:27:19Z")

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Not that you can also change

> (gdb) hb main

to

> (gdb) thb main

to have a _temporary_ breakpoint at main() that still leaves the two hardware breakpoints for single stepping.
