Hi, I’m an engineer with Futurewei Technologies, Michael Brothers.
We have made a big push towards accelerating the establishment of the open source RISCV verification ecosystem.
We have open sourced our RISCV instruction stream generator with the OHW group and have modified Spike into an API form suitable for lock-step co-simulation with the generator:
The API is called Handcar, continuing the railroad theme in the name Spike.
It adds a sparse memory model to Spike, a register (FP, XPR, Vector, CSR) API, a memory API and some others.
Please take a look! Thanks!
Coming soon is an update to the public release as we continue to actively track upstream changes in Spike as well as add features to the generator itself.