Fu740 PLL's not locking?

HiFive Unmatched
1

Hi, all,

Per the fu740-c000-manual-v1p2, p. 84, when I set PRCI's core_pllcfg pllr, pllf and pllq fields to 0, 76 and 2 respectively, and busywait on pll_config's plllock bit, it’s always 0. I assume it’s not active low, correct?

I tried a couple of other PLL’s (ethernet and DDR) and got the same result.

Another engineer I reached out to using the unmatched board also independently reported having the same issue with PLL’s never locking.

I then looked through the u-boot code and IIUC, it appears to be delaying 70us and then blindly continuing, rather than waiting on the PLL lock.

I was wondering if anyone could confirm that the PLL locks on the fu740 flip to 1 once the PLL is stable? Bonus if you can point me to a code snippet showing how they should be exercised (for, say, core_pllcfg).

Thank you!

2

There is an old forum post for the fe310 that might be relevant.
https://forums.sifive.com/t/something-i-learned-about-the-cpu-clock/2635

It points to some freedom-e-sdk code at the end. Here is the source code for that.
https://github.com/sifive/freedom-metal/blob/master/src/drivers/sifive_fe310-g000_pll.c#L344

This is a very different SoC, but it might be the same PLL subsystem so this might be relevant.

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3

I see the PLL’s for core and DDR are locked when reading pllcfg from FUSDK Linux using:

devmem2  0x10000004 w
  0x820544C2

devmem2  0x1000000c w
  0x820544C2

I’m looking at bit 31 in the registers which is the PLL lock status and it’s high.

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4

I’m told that the lock bit may not be reliable and can be ignored, if you wait the maximum amount of time that a lock should take, which is 70us in the worst case.

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