Per the fu740-c000-manual-v1p2, p. 84, when I set
pllq fields to 0, 76 and 2 respectively, and busywait on
plllock bit, it’s always 0. I assume it’s not active low, correct?
I tried a couple of other PLL’s (ethernet and DDR) and got the same result.
Another engineer I reached out to using the unmatched board also independently reported having the same issue with PLL’s never locking.
I then looked through the
u-boot code and IIUC, it appears to be delaying 70us and then blindly continuing, rather than waiting on the PLL lock.
I was wondering if anyone could confirm that the PLL locks on the fu740 flip to 1 once the PLL is stable? Bonus if you can point me to a code snippet showing how they should be exercised (for, say,