# FU740-C000 PCIe X8 AXI4 Subsystem - configuration x2/x2/x2/x2 **URL:** \ **Category:** HiFive Unmatched\ **Created:** [July 9, 2021, 9:22pm UTC](https://forums.sifive.com/t/fu740-c000-pcie-x8-axi4-subsystem-configuration-x2-x2-x2-x2/4951 "2021-07-09T21:22:58Z")\ **Posts on this page:** 8\ **Page:** 1
**Author:** ![StefanAEET](https://avatars.discourse-cdn.com/v4/letter/s/919ad9/32.png) [@StefanAEET](https://forums.sifive.com/u/StefanAEET)\ **Post date:** [July 9, 2021, 9:22pm UTC](https://forums.sifive.com/t/fu740-c000-pcie-x8-axi4-subsystem-configuration-x2-x2-x2-x2/4951/1 "2021-07-09T21:22:58Z")
There is no information about PCIe lane configurations. Presumably it is 1 lane x8. Is it possible to have 4 lanes each x2 ---
**Author:** ![cavemanol](https://avatars.discourse-cdn.com/v4/letter/c/ac91a4/32.png) [@cavemanol](https://forums.sifive.com/u/cavemanol)\ **Post date:** [July 10, 2021, 3:42am UTC](https://forums.sifive.com/t/fu740-c000-pcie-x8-axi4-subsystem-configuration-x2-x2-x2-x2/4951/2 "2021-07-10T03:42:36Z")
On the product brief, the following layout for PCIe lanes is given. ![PCIeLanes](https://us1.discourse-cdn.com/flex020/uploads/sifive/original/2X/f/f172a8add4bc63b9ed062163912b85be8734f072.png) It shows the PCIe slot is x8 only, but also the PCIe switch only has an x8 connection to the CPU which shared with the SSD, wifi/BT, and USB ports. I haven’t found anything on configuring a specific lane allocation for each PCIe connection to the switch. Also, the schematics show the same PCIe layout. ---
**Author:** ![StefanAEET](https://avatars.discourse-cdn.com/v4/letter/s/919ad9/32.png) [@StefanAEET](https://forums.sifive.com/u/StefanAEET)\ **Post date:** [July 10, 2021, 3:03pm UTC](https://forums.sifive.com/t/fu740-c000-pcie-x8-axi4-subsystem-configuration-x2-x2-x2-x2/4951/3 "2021-07-10T15:03:09Z")
Hello Oliver We are working on an embedded application with FU740-C000. The **HiFive Unmatched** will be a starting point, but we have to optimize it and reduce cost. Based on this link, the PCIe controller is an IP from Synopsys [[v4,4/6] dt-bindings: PCI: Add SiFive FU740 PCIe host controller - Patchwork (kernel.org)](https://patchwork.kernel.org/project/linux-riscv/patch/20210401060054.40788-5-greentime.hu@sifive.com/) SiFive FU740 PCIe host controller is based on the Synopsys DesignWare PCI core. Next step will be to get the datasheet/SW application manuals from Synopsys and understand the configuration registers. If anybody could have experience with this PCI core, please share with us. ![FU740-C000-Synopsys-PCIe](https://us1.discourse-cdn.com/flex020/uploads/sifive/original/2X/e/ef26370da63e2b59c49499e9e899b13b618aa12c.png) ---
**Author:** ![jimw](https://avatars.discourse-cdn.com/v4/letter/j/f14d63/32.png) [@jimw](https://forums.sifive.com/u/jimw)\ **Post date:** [July 10, 2021, 5:39pm UTC](https://forums.sifive.com/t/fu740-c000-pcie-x8-axi4-subsystem-configuration-x2-x2-x2-x2/4951/4 "2021-07-10T17:39:46Z")
If you are asking about PCIe bifurcation, I think I saw a comment somewhere that said it wasn’t supported. I don’t know anything about PCIe myself. I don’t know if this is missing hardware support or missing firmware support or missing driver support or what. ---
**Author:** ![StefanAEET](https://avatars.discourse-cdn.com/v4/letter/s/919ad9/32.png) [@StefanAEET](https://forums.sifive.com/u/StefanAEET)\ **Post date:** [July 10, 2021, 6:29pm UTC](https://forums.sifive.com/t/fu740-c000-pcie-x8-axi4-subsystem-configuration-x2-x2-x2-x2/4951/5 "2021-07-10T18:29:12Z")
Thank you, Jim, Looks like this is the definition of configuration we are asking for. At this time the Synopsys’ PCIe “IP datasheet” is the origin of information. Will create account to the Synopsys’s support and will request the datasheet. Also will ask the SiFive’s support to confirm the exact IP reference number. ---
**Author:** ![qz3fwd](https://avatars.discourse-cdn.com/v4/letter/q/77aa72/32.png) [@qz3fwd](https://forums.sifive.com/u/qz3fwd)\ **Post date:** [July 11, 2021, 12:14am UTC](https://forums.sifive.com/t/fu740-c000-pcie-x8-axi4-subsystem-configuration-x2-x2-x2-x2/4951/6 "2021-07-11T00:14:40Z")
I had asked if the PCIE port supported bifurcation and got someone replying to the effect that probably nobody had written (driver) support for it so no. ---
**Author:** ![StefanAEET](https://avatars.discourse-cdn.com/v4/letter/s/919ad9/32.png) [@StefanAEET](https://forums.sifive.com/u/StefanAEET)\ **Post date:** [July 11, 2021, 1:06am UTC](https://forums.sifive.com/t/fu740-c000-pcie-x8-axi4-subsystem-configuration-x2-x2-x2-x2/4951/7 "2021-07-11T01:06:02Z")
Thank you The driver is software, so it could be updated. The IP hardware from Synopsys is hardware and if there is no bifurcation possible this mean NO ---
**Author:** ![StefanAEET](https://avatars.discourse-cdn.com/v4/letter/s/919ad9/32.png) [@StefanAEET](https://forums.sifive.com/u/StefanAEET)\ **Post date:** [July 13, 2021, 5:19pm UTC](https://forums.sifive.com/t/fu740-c000-pcie-x8-axi4-subsystem-configuration-x2-x2-x2-x2/4951/8 "2021-07-13T17:19:37Z")
I have this document from Synopsys dwc\_pcie\_csds.pdf PCI Express Complete Solution from Synopsys On page 3 there is a following description: " PIPE bifurcation as well as PHY macro aggregation for x1 to x16 PHY configurations" How we could contact a technical support from SuFuve to confirm this functionality in FU740