# FreedomStudio FESPI\_WRITE\_REG error

**URL:** <https://forums.sifive.com/t/freedomstudio-fespi-write-reg-error/1145>\
**Category:** General\
**Created:** [April 8, 2018, 9:22am UTC](https://forums.sifive.com/t/freedomstudio-fespi-write-reg-error/1145 "2018-04-08T09:22:53Z")\
**Posts on this page:** 3\
**Page:** 1

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**Author:** ![cailinlin](https://avatars.discourse-cdn.com/v4/letter/c/46a35a/32.png) [@cailinlin](https://forums.sifive.com/u/cailinlin)\
**Post date:** [April 8, 2018, 9:22am UTC](https://forums.sifive.com/t/freedomstudio-fespi-write-reg-error/1145/1 "2018-04-08T09:22:53Z")

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Hi, everyone!  
When I use FreedomStudio debug sample code “global\_interrupts”, the following error occurs:

Open On-Chip Debugger 0.10.0+dev-g2c183e3-dirty (2018-01-03-10:25)  
Licensed under GNU GPL v2  
For bug reports, read  
[http://openocd.org/doc/doxygen/bugs.html](http://openocd.org/doc/doxygen/bugs.html)  
adapter speed: 10000 kHz  
Info : auto-selecting first available session transport “jtag”. To override use 'transport select '.  
Info : ftdi: if you experience problems at higher adapter clocks, try the command "ftdi\_tdo\_sample\_edge falling"  
Info : clock speed 10000 kHz  
Info : JTAG tap: riscv.cpu tap/device found: 0x20000913 (mfg: 0x489 (SiFive, Inc.), part: 0x0000, ver: 0x2)  
Info : dtmcontrol\_idle=5, dmi\_busy\_delay=1, ac\_busy\_delay=0  
Info : dtmcontrol\_idle=5, dmi\_busy\_delay=2, ac\_busy\_delay=0  
Info : dtmcontrol\_idle=5, dmi\_busy\_delay=3, ac\_busy\_delay=0  
Info : dtmcontrol\_idle=5, dmi\_busy\_delay=4, ac\_busy\_delay=0  
Info : Disabling abstract command reads from CSRs.  
Info : Disabling abstract command writes to CSRs.  
Info : [0] Found 2 triggers  
Info : Examined RISC-V core; found 1 harts  
Info : hart 0: XLEN=32, 2 triggers  
Info : Listening on port 3333 for gdb connections  
Error: FESPI\_WRITE\_REG error  
Error: auto\_probe failed

I do not know how to solve this problem, Can you help me to solve it?  
Thanks!

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**Author:** ![mwachs5](https://sea2.discourse-cdn.com/flex020/user_avatar/forums.sifive.com/mwachs5/32/13_2.png) [@mwachs5](https://forums.sifive.com/u/mwachs5)\
**Post date:** [April 9, 2018, 8:47pm UTC](https://forums.sifive.com/t/freedomstudio-fespi-write-reg-error/1145/2 "2018-04-09T20:47:49Z")

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Are you sure you are using a project targeting the right platform? For example, if you are using the HiFive1, did you import the HiFive1 projects?

(The `FESPI_WRITE_REG` error makes it look like you’re pointint to the wrong `openocd.cfg` file, because it’s pointing to the wrong place for the `flash bank` command.)

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**Author:** ![cailinlin](https://avatars.discourse-cdn.com/v4/letter/c/46a35a/32.png) [@cailinlin](https://forums.sifive.com/u/cailinlin)\
**Post date:** [April 10, 2018, 2:42am UTC](https://forums.sifive.com/t/freedomstudio-fespi-write-reg-error/1145/3 "2018-04-10T02:42:20Z")

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Thanks for your reply!

I fix some FPGA configuration files of Freedom code and generate bit file, then put on Nexys4 DDR.

On the basis of this, I import the E31 Arty projects, and I fix the expected-id of .cfg file.

I don’t fix flash bank comand. I think Nexys4 DDR and Arty board flash bank should be same.If there should be fix with flash bank, can you give some suggestion, I don’t know how to fix it.

Thanks!