# Freedom E300 RTL Synthesis in Artix-7 AC701

**URL:** <https://forums.sifive.com/t/freedom-e300-rtl-synthesis-in-artix-7-ac701/4082>\
**Category:** SiFive Core Designer\
**Created:** [October 2, 2020, 11:32am UTC](https://forums.sifive.com/t/freedom-e300-rtl-synthesis-in-artix-7-ac701/4082 "2020-10-02T11:32:42Z")\
**Posts on this page:** 1\
**Page:** 1

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**Author:** ![Tonmoy](https://avatars.discourse-cdn.com/v4/letter/t/e36b37/32.png) [@Tonmoy](https://forums.sifive.com/u/Tonmoy)\
**Post date:** [October 2, 2020, 11:32am UTC](https://forums.sifive.com/t/freedom-e300-rtl-synthesis-in-artix-7-ac701/4082/1 "2020-10-02T11:32:42Z")

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Hello,  
I am a student . I have generated the SiFive Freedom E300 RTL Verilog code with Ubuntu and copy the source code to Centos 7, where my Vivado is installed. But when I generate the bitstream with Vivado and program the Artix-7 AC701, the UART does not display the SiFive message it should display in the serial communication terminal. I am looking for a possible solution.