# FE310-G000 dminfo openocd

**URL:** <https://forums.sifive.com/t/fe310-g000-dminfo-openocd/1323>\
**Category:** Freedom E300\
**Created:** [June 20, 2018, 4:02am UTC](https://forums.sifive.com/t/fe310-g000-dminfo-openocd/1323 "2018-06-20T04:02:13Z")\
**Posts on this page:** 4\
**Page:** 1

<div class="post-metadata">

**Author:** ![dwelch](https://sea2.discourse-cdn.com/flex020/user_avatar/forums.sifive.com/dwelch/32/863_2.png) [@dwelch](https://forums.sifive.com/u/dwelch)\
**Post date:** [June 20, 2018, 4:02am UTC](https://forums.sifive.com/t/fe310-g000-dminfo-openocd/1323/1 "2018-06-20T04:02:13Z")

</div>

I have a breakout board with one of these parts on it, and am trying to get into the part via jtag via openocd.

interface ftdi  
ftdi\_vid\_pid 0x0403 0x6014  
ftdi\_layout\_init 0x0008 0x00fb

#D0 TCK  
#D1 TDI  
#D2 TDO  
#D3 TMS

adapter\_khz 10000  
telnet\_port 4444  
gdb\_port 0  
tcl\_port 0

set \_CHIPNAME riscv  
jtag newtap $\_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913

set \_TARGETNAME $\_CHIPNAME.cpu  
target create $\_TARGETNAME riscv -chain-position $\_TARGETNAME  
$\_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1

#flash bank my\_first\_flash fespi 0x20000000 0 0 0 $\_TARGETNAME  
#flash protect 0 64 last off

using an adafruit FT232H breakout. making progress as others have but I dont see an answer to the problem.

Open On-Chip Debugger 0.10.0+dev-00382-g5d9f486 (2018-06-19-19:02)  
Licensed under GNU GPL v2  
For bug reports, read  
[OpenOCD: Bug Reporting](http://openocd.org/doc/doxygen/bugs.html)  
adapter speed: 10000 kHz  
Info : auto-selecting first available session transport “jtag”. To override use ‘transport select ’.  
1  
Info : Listening on port 39839 for tcl connections  
Info : Listening on port 4444 for telnet connections  
Info : ftdi: if you experience problems at higher adapter clocks, try the command “ftdi\_tdo\_sample\_edge falling”  
Info : clock speed 10000 kHz  
Info : JTAG tap: riscv.cpu tap/device found: 0x10e31913 (mfg: 0x489 (SiFive, Inc.), part: 0x0e31, ver: 0x1)  
Error: OpenOCD only supports Debug Module version 1, not 0 (dminfo=0x0)  
Info : Listening on port 42117 for gdb connections

and of course then

telnet localhost 4444  
Trying 127.0.0.1…  
Connected to localhost.  
Escape character is ‘^]’.  
Open On-Chip Debugger

> halt  
> Target not examined yet

How do I/we get past this error:

Error: OpenOCD only supports Debug Module version 1, not 0 (dminfo=0x0)

Is it an openocd thing is it a chip configuration thing do I need to strap the pins differently? What am I missing?

---

<div class="post-metadata">

**Author:** ![mwachs5](https://sea2.discourse-cdn.com/flex020/user_avatar/forums.sifive.com/mwachs5/32/13_2.png) [@mwachs5](https://forums.sifive.com/u/mwachs5)\
**Post date:** [June 20, 2018, 1:39pm UTC](https://forums.sifive.com/t/fe310-g000-dminfo-openocd/1323/2 "2018-06-20T13:39:27Z")

</div>

Are you inadvertently controlling the System Reset pin as well, or did you really only connect the 4 JTAG pins you mentioned? Most JTAG connectors also include a system reset (and sometimes TRST, which doesn’t matter) connection.

It looks like your chip is being held in reset.

---

<div class="post-metadata">

**Author:** ![dwelch](https://sea2.discourse-cdn.com/flex020/user_avatar/forums.sifive.com/dwelch/32/863_2.png) [@dwelch](https://forums.sifive.com/u/dwelch)\
**Post date:** [June 20, 2018, 3:12pm UTC](https://forums.sifive.com/t/fe310-g000-dminfo-openocd/1323/3 "2018-06-20T15:12:16Z")

</div>

I can use a reset from the ftdi, but have historically never needed it to do jtag. It would need to connect to something on the chip which I tend to control separately.

I have AON ERST N strapped high, deasserted. but have pulled it either way with no change in results. I do not see another reset in the datasheet, am I missing one?

---

<div class="post-metadata">

**Author:** ![dwelch](https://sea2.discourse-cdn.com/flex020/user_avatar/forums.sifive.com/dwelch/32/863_2.png) [@dwelch](https://forums.sifive.com/u/dwelch)\
**Post date:** [June 26, 2018, 5:51pm UTC](https://forums.sifive.com/t/fe310-g000-dminfo-openocd/1323/4 "2018-06-26T17:51:00Z")

</div>

I did not provide an external clock to the device, there is an internal clock, I do not need an external clock correct?

Is there a minimal reference design, the minimum you need to get the part working? No crystal/clock no spi flash, etc? Power, caps, jtag?

Thanks,  
David