# External Debugger with HiFive1 Rev B

**URL:** <https://forums.sifive.com/t/external-debugger-with-hifive1-rev-b/5483>\
**Category:** HiFive1 Rev B\
**Created:** [December 10, 2021, 11:18pm UTC](https://forums.sifive.com/t/external-debugger-with-hifive1-rev-b/5483 "2021-12-10T23:18:02Z")\
**Posts on this page:** 2\
**Page:** 1

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**Author:** ![aggarg](https://sea2.discourse-cdn.com/flex020/user_avatar/forums.sifive.com/aggarg/32/1450_2.png) [@aggarg](https://forums.sifive.com/u/aggarg)\
**Post date:** [December 10, 2021, 11:18pm UTC](https://forums.sifive.com/t/external-debugger-with-hifive1-rev-b/5483/1 "2021-12-10T23:18:02Z")

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I want to use Segger JLink Ultra debug probe to debug HiFive1 Rev B. The board has Segger OB which seems to interfere with the external debugger. I contacted Segger and I was told that there is no non-intrusive way to use an external probe with this board - [SiFive HiFive1 - SEGGER Wiki](https://wiki.segger.com/SiFive_HiFive1).

I am looking for an intrusive way to be able to use external probe. I tried to connect TP4 to GND to hold the Segger OB in reset but that does not seem to work. Does anyone know a way to use an external debug probe? Would de-soldering R24, R25 and R26 help?

Thanks.

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**Author:** ![pds](https://avatars.discourse-cdn.com/v4/letter/p/8edcca/32.png) [@pds](https://forums.sifive.com/u/pds)\
**Post date:** [December 21, 2021, 8:37pm UTC](https://forums.sifive.com/t/external-debugger-with-hifive1-rev-b/5483/2 "2021-12-21T20:37:04Z")

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Hi @aggarg Gautav, welcome! That’s an excellent question.

Great idea to use TP4 ([schematic](https://sifive.cdn.prismic.io/sifive/c34f4c7f-0d3a-493e-8a19-a0b18f8a4555_hifive1-b01-schematics.pdf) on sheet 4, U3-34, DBG\_RST), and **hold TP4 low** , so that U3 _might_ keep all of its I/O lines as inputs or otherwise floating states without disturbing the target FE310 chip. Apparently this was not the case.

Did you try **not connecting** the micro-usb cable at J5? If U3 doesn’t see any USB activity, it might go to a dormant or sleeping state and also float its outputs.

Removing R24, R25, and R26 is probably **not** enough; you would most likely have to separate the JTAG\_SRST line by cutting the trace from U3-64 (hoping there’s no via underneath U3). Unfortunately, HiFive has no easy series resistor on the JTAG\_SRST line to remove.

The TP4 signal is also available at J9-3, which is a really neat set of test points for use with a quick connect pogo pin cable such as [tag-connect](https://www.tag-connect.com/product/tc2030-ctx-nl-6-pin-no-legs-cable-with-10-pin-micro-connector-for-cortex-processors)

To see how U3 handles its DBG\_RST input, check with a scope on its output lines DBG\_TGT\_TDI, \_TCK, and \_TMS. This might give a clue of U3’s various states of operation. Hopefully, you can find some mode or perhaps even unmentioned input pin which keeps the PTD7 output (JTAG\_SRST) in a floating state, and not similarly pulled low.

Also interesting is this reference: [Segger, JLink, and the U3 (MK22FN128VLH10)](https://www.segger.com/downloads/jlink/UM08034_JLinkOBK22.pdf)