# Error in downloading the vcu118 bitstream by vivado 2018.2
**URL:** https://forums.sifive.com/t/error-in-downloading-the-vcu118-bitstream-by-vivado-2018-2/3009
**Category:** Freedom U500
**Created:** [November 5, 2019, 5:37am UTC](https://forums.sifive.com/t/error-in-downloading-the-vcu118-bitstream-by-vivado-2018-2/3009 "2019-11-05T05:37:32Z")
**Posts on this page:** 2
**Page:** 1
### Author:  [@andrewZhu](https://forums.sifive.com/u/andrewZhu)
#### Post date: [November 5, 2019, 5:37am UTC](https://forums.sifive.com/t/error-in-downloading-the-vcu118-bitstream-by-vivado-2018-2/3009/1 "2019-11-05T05:37:32Z")
Hi,
The vivado version of my compilation environment is 2018.2, and compile the vcu118 with Makefile.vcu118-u500devkit. The following error occurred during downloading bitstream with vivado:
**open\_hw\_target**
**current\_hw\_device [get\_hw\_devices xcvu9p\_0]**
**refresh\_hw\_device -update\_hw\_probes false [lindex [get\_hw\_devices xcvu9p\_0] 0]**
**INFO: [Labtools 27-1434] Device xcvu9p (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.**
**WARNING: [Labtools 27-3361] The debug hub core was not detected.**
\*\*Resolution: \*\*
**1. Make sure the clock connected to the debug hub (dbg\_hub) core is a free running clock and is active.**
**2. Make sure the BSCAN\_SWITCH\_USER\_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device. To determine the user scan chain setting in the design, open the implemented design and use ‘get\_property C\_USER\_SCAN\_CHAIN [get\_debug\_cores dbg\_hub]’.**
**For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).**
**set\_property PROBES.FILE {} [get\_hw\_devices xcvu9p\_0]**
**set\_property FULL\_PROBES.FILE {} [get\_hw\_devices xcvu9p\_0]**
**set\_property PROGRAM.FILE {/freedom/builds/vcu118-u500devkit/obj/VCU118Shell.bit} [get\_hw\_devices xcvu9p\_0]**
**program\_hw\_devices [get\_hw\_devices xcvu9p\_0]**
**ERROR: [Labtools 27-3303] Incorrect bitstream assigned to device. Bitstream was generated for part xcvu9p-flga2104-2L-e, target device (with IDCODE revision 0) is compatible with es1 revision bitstreams.**
**To allow the bitstream to be programmed to the device, use “set\_param xicom.use\_bitstream\_version\_check false” tcl command.**
**INFO: [Labtools 27-3164] End of startup status: HIGH**
**ERROR: [Common 17-39] ‘program\_hw\_devices’ failed due to earlier errors.**
According to the prompt, no more errors will occur after executing the following statement, but an warning will occur:
set\_param xicom.use\_bitstream\_version\_check false
0
set\_property PROBES.FILE {} [get\_hw\_devices xcvu9p\_0]
set\_property FULL\_PROBES.FILE {} [get\_hw\_devices xcvu9p\_0]
set\_property PROGRAM.FILE {/freedom/builds/vcu118-u500devkit/obj/VCU118Shell.bit} [get\_hw\_devices xcvu9p\_0]
program\_hw\_devices [get\_hw\_devices xcvu9p\_0]
WARNING: [Xicom 50-99] Incorrect bitstream assigned to device. Bitstream was generated for part xcvu9p-flga2104-2L-e, target device (with IDCODE revision 0) is compatible with es1 revision bitstreams.
INFO: [Labtools 27-3164] End of startup status: HIGH
program\_hw\_devices: Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 6895.848 ; gain = 0.000 ; free physical = 378710 ; free virtual = 773686
refresh\_hw\_device [lindex [get\_hw\_devices xcvu9p\_0] 0]
WARNING: [Labtools 27-3089] Calibration is still in-progress.
INFO: [Labtools 27-2302] Device xcvu9p (JTAG device index = 0) is programmed with a design that has 1 MIG core(s).
INFO: [Labtools 27-3143] Calibration status change detected, refreshing MIG\_1
**Is this vivado version incompatible with freedom or something else?**
---
### Author:  [@andrewZhu](https://forums.sifive.com/u/andrewZhu)
#### Post date: [November 6, 2019, 12:50am UTC](https://forums.sifive.com/t/error-in-downloading-the-vcu118-bitstream-by-vivado-2018-2/3009/2 "2019-11-06T00:50:54Z")
I have contacted the FAE of Xilinx. Because the FPGA on vcu118 development board is an ES1, that is, engineering sample.