# E31 evaluation simulation
**URL:** https://forums.sifive.com/t/e31-evaluation-simulation/689
**Category:** SiFive RISC-V Core IP Evaluation
**Created:** [August 15, 2017, 6:44am UTC](https://forums.sifive.com/t/e31-evaluation-simulation/689 "2017-08-15T06:44:54Z")
**Posts on this page:** 8
**Page:** 1
### Author:  [@ling](https://forums.sifive.com/u/ling)
#### Post date: [August 15, 2017, 6:44am UTC](https://forums.sifive.com/t/e31-evaluation-simulation/689/1 "2017-08-15T06:44:54Z")
hello, I have some question for the E31 rtl simulation, I try to use toolchain to generate hex file, and I write a timer interrupt program , but when I use vcs to simulate the E31 rtl with this program, I find that when the program try to access the address 0x02004000(the TIMER\_CMP),the value of PC will jump into zero, what’s wrong with it ???
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### Author:  [@DrewatSiFive](https://forums.sifive.com/u/DrewatSiFive)
#### Post date: [August 15, 2017, 2:12pm UTC](https://forums.sifive.com/t/e31-evaluation-simulation/689/2 "2017-08-15T14:12:29Z")
Can you share the source code?
Do you set mtvec in your application? It could be that you are taking a trap prior to setting up the trap entry/exit.
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### Author:  [@ling](https://forums.sifive.com/u/ling)
#### Post date: [August 16, 2017, 1:12am UTC](https://forums.sifive.com/t/e31-evaluation-simulation/689/3 "2017-08-16T01:12:08Z")
yes, I see the bsp package have set mtvec at init.c
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### Author:  [@ling](https://forums.sifive.com/u/ling)
#### Post date: [August 16, 2017, 9:30am UTC](https://forums.sifive.com/t/e31-evaluation-simulation/689/4 "2017-08-16T09:30:03Z")
but I just access the address 0x0200\_0000,why it will produce a trap ??
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### Author:  [@mwachs5](https://forums.sifive.com/u/mwachs5)
#### Post date: [August 16, 2017, 4:29pm UTC](https://forums.sifive.com/t/e31-evaluation-simulation/689/5 "2017-08-16T16:29:46Z")
What do you mean you are “accessing” the address? Are you reading, writing? Are you using the proper size access (lw, lh, lb, ld?) If you write the TIMER\_CMP value, then it’s quite likely you take an interrupt which you may not have set up properly. Can you share the code that is causing the trap?
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### Author:  [@DrewatSiFive](https://forums.sifive.com/u/DrewatSiFive)
#### Post date: [August 16, 2017, 4:29pm UTC](https://forums.sifive.com/t/e31-evaluation-simulation/689/6 "2017-08-16T16:29:58Z")
Address 0x0200\_0000 is the Machine Software Pending register in the CLINT. If you write a 1 to the LSB of this register, and software interrupts are enabled in the _mie_, then this will cause a trap.
Without seeing your code, we don’t know for sure what is going on. What I wrote above is simply one possibility.
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### Author:  [@ling](https://forums.sifive.com/u/ling)
#### Post date: [August 17, 2017, 1:18am UTC](https://forums.sifive.com/t/e31-evaluation-simulation/689/7 "2017-08-17T01:18:01Z")
thank you for your answer, I have solve the problem,but sometimes, I try to write the address 0x3000\_0000 that is the periphery device region, It also produce a trap, why ?
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### Author:  [@ling](https://forums.sifive.com/u/ling)
#### Post date: [August 17, 2017, 1:54pm UTC](https://forums.sifive.com/t/e31-evaluation-simulation/689/8 "2017-08-17T13:54:19Z")
yes,I write the address, and it take a trap but not a interrupt