I have a question after read the E31 coreplex document . In the document RISC-V ISA Volumn 2,the 12th-31th bits of CSR mie is WPRI,why do use it as the local interrupt enable bit in E31 coreplex ?
In version 1.10 of the RISC-V Privilege Specification, section 7.2.1 calls out:
Additional non-standard local interrupt sources can be made visible to machine-mode by adding them to the high bits of the mip/mie registers, with corresponding additional cause values returned in the mcause register.
Also in the working draft of the Privilege Spec (https://github.com/riscv/riscv-isa-manual) there is additional language in the mip/mie section regarding the most significant bits in this register.
is it say that the local interrupt is added at E31 EVAL ??
Yes, in the E31 Coreplex Evaluation RTL, there is an input
io_local_interrupts_0[15:0], which are the interrupt sources connected to bits [31:16] of MIP/MIE registers in the core.