DUMB question about CSRs


(Ray Bahr) #1

Hi All,

I am trying to find an include file that has predefined the ‘current’ list of CSRs and their register numbers. This is to import to a C program and dump / set them.

I have seen registers such as ‘mcycle’ apparently defined - as in this won’t cause an error, BUT I can’t find the source!

Thanks

Ray


(mara) #2

The linux kernel;s csr.h header has quite a lot of CSR definitions ( https://github.com/torvalds/linux/blob/master/arch/riscv/include/asm/csr.h ). The complete current list (of what is defined, not necessarily implemented on every SoC) can be found in the RISC-V privileged specification.


(Jim Wilson) #3

The assembler has a list of csrs, because it needs to be able to assemble them. In the binutils source tree, see the DECLARE_CSR macros in the include/opcode/riscv-opc.h file. Note that this is an internal interface, and is subject to change in future binutils versions.

The github.com/riscv/riscv-opcodes module has info on csrs. The parse-opcodes file is a python script that has a list of csrs with names and addresses. This is meant to be used to generate header files and is part of the riscv-tools repo. There might be a usable list of csrs somewhere in riscv-tools.

As the previous poster mentioned, the privilege spec is the best place to look, and most SOCs only implement a subset of the CSRs. Also, the list of CSRs changes occasionally, as the spec is still evolving. Some proposed extensions will add new CSRs for instance. Different architecture versions have different csr lists, and csr addresses have changed in the past, but hopefully not anymore.


(Ray Bahr) #4

Thanks All,

I will look at these!

Ray


(Ray Bahr) #5

Hi All,

Been looking through all the code associated with the unleashed board, and have not found anywhere the register set is defined. This also means that I don’t know which registers are used by the Unleashed device.

Any help understanding this would be greatly appreciated.

Thanks

Ray


(Jim Wilson) #6

I don’t know of any concise list of implemented CSRs, but if you look at sifive.com/documentation you can find a pdf for the Freedom U540-C000 which is the ASIC used on the freedom unleashed board, and it has chapters that list various features and the CSRs and memory mapped I/O registers that you can use to control them. There is also a memory map chapter that describes all of the memory mapped I/O regions.

Is there a reason why you need a list of CSRs? Most CSRs are optional, and most chips only implement a subset of them, that may change from one version of the chip to the next. Also, some CSRs are supported, but implemented via a trap handler that reads a memory mapped I/O region, so whether we support it or not depends on what exactly you mean by “supported”. An example of this is mtime, which is implemented off chip via memory mapped I/O, but is claimed to be supported, and is used by the linux kernel. If you want to be safe and portable, you need to probe to detect which CSRs are available. Though there is probably a minimal set required by the linux kernel, but that should be documented in the linux kernel, not in the processor docs.


(Ray Bahr) #7

I was looking at mtime and was not understanding what I saw.