Don't fear the bricking (unbricking Unmatched via JTAG)

HiFive Unmatched
2

Very nice idea here, @Maquefel
To expand a bit on the idea let me suggest a few more lines to add, immediately following the target create step. These will give a very useful log of all progress steps that OpenOCD goes through. ToDo: Expand the idea for multiple harts.

riscv.cpu.0 configure -event examine-start {
  echo "examine start"

  # prevent the dreaded 'Error: unable to halt hart 0' message
  if {[catch {riscv.cpu.0 arp_examine} err] != 0} {
    asic_reset
    riscv.cpu.0 arp_examine
  }
}

proc asic_reset { } {
  echo "proc asic_reset"

  # pulse the reset line just in case h/w was locked
  #!!!CRITICAL -- to avoid dreaded 'Error: unable to halt hart 0' message during init ...

  echo "asic_reset: pulsing reset line"
  #------------------------
  reset_config trst_only trst_open_drain separate
  jtag_ntrst_assert_width 0
  jtag_ntrst_delay 0
  adapter assert trst  ;#  ftdi_set_signal nTRST 0  ;# assert RST
  adapter deassert trst  ;#  ftdi_set_signal nTRST 1  ;# deassert RST
  reset_config none
  #------------------------

  jtag arp_init-reset  ;# this thing takes a long time to come back

  echo "asic_reset: wait for target get into reset state (prevent impatient scan retries)"
  sleep 1500  ;# ASIC target AON reset block delay, typical default 2^8 cycles of core clock
}

proc jtag_init { } {  ;# overrides openocd/src/jtag/startup.tcl
  echo "proc jtag_init"
  if {[catch {jtag arp_init} err] != 0} {
    asic_reset
  }
}

proc init_reset { mode } {  ;# overrides openocd/src/jtag/startup.tcl
  echo "proc init_reset"
  if {[catch {jtag arp_init} err] != 0} {
    asic_reset
  }
}

riscv.cpu.0 configure -event examine-end { echo "examine end" }
riscv.cpu.0 configure -event examine-fail { echo "examine fail ... OOPS!" }

riscv.cpu.0 configure -event reset-start { echo "reset start" }
riscv.cpu.0 configure -event reset-assert-pre { echo "reset assert pre" }
riscv.cpu.0 configure -event reset-assert { echo "reset assert" }
riscv.cpu.0 configure -event reset-assert-post { echo "reset assert post" }
riscv.cpu.0 configure -event reset-deassert-pre { echo "reset deassert pre" }
riscv.cpu.0 configure -event reset-deassert-post { echo "reset deassert post" }
riscv.cpu.0 configure -event reset-end { echo "reset end" }

riscv.cpu.0 configure -event debug-halted { echo "debug halted" }
riscv.cpu.0 configure -event debug-resumed { echo "debug resumed" }
riscv.cpu.0 configure -event resume-start { echo "resume start" }
riscv.cpu.0 configure -event resume-end { echo "resume end" }

riscv.cpu.0 configure -event step-start { echo "step start" }
riscv.cpu.0 configure -event step-end { echo "step end" }

riscv.cpu.0 configure -event gdb-attach { echo "gdb attach" }
riscv.cpu.0 configure -event gdb-detach { echo "gdb detach" }

riscv.cpu.0 configure -event gdb-halt { echo "gdb halt" }
riscv.cpu.0 configure -event gdb-start { echo "gdb start" }
riscv.cpu.0 configure -event gdb-end { echo "gdb end" }

riscv.cpu.0 configure -event gdb-flash-erase-start { echo "gdb flash erase start" }
riscv.cpu.0 configure -event gdb-flash-erase-end { echo "gdb flash erase end" }
riscv.cpu.0 configure -event gdb-flash-write-start { echo "gdb flash write start" }
riscv.cpu.0 configure -event gdb-flash-write-end { echo "gdb flash write end" }

For lightweight operation when a debugger interactive session is not needed, you can add the following three tcl statements somewhere before the transport selection; then optionally specify one or more at the command line level (with -c option) when interactivity is desired.

gdb_port disabled  ;# 3333
tcl_port disabled  ;# 6666
telnet_port disabled  ;# 4444

For some more tips dealing with FTDI adapter configuration and the tiny glitch bug, see also Progress getting OpenOCD usable with RevB