Does ACAP pose a risk to RISC-V?

I recently read this article on Xilinx’s new architecture which ends with the following quotation:

“The world of CPU-centric computing is over. It’s well understood that the future of computing is going to be more of a heterogeneous architecture where there will be accelerators somewhere in the system or the datacenter. It’s as much driven by the nature of the workload and the exponential increase in that, as well as the fact that Moore’s Law really has been slowing down if not completely stopped working. It’s certainly has stopped working from an economic perspective, even though we know how to scale to the next process node, from an economic perspective that everything is getting better, faster, cheaper, that’s really not working anymore, and actually hasn’t been working for a few nodes. What that means is that in this new era, architecture will be heterogeneous with accelerators.”

I understand that to mean ISA’s might soon be a thing of the past, with ACAP virtually creating the achitechture on the fly based on the programming.

Am I completely wrong?

This is Xilinx PR trying to make the self serving claim that Xilinx is the future. Move along, nothing to see here. Code requires an ISA.


I’d expand on that answer.

First, Moore’s law isn’t over yet (behold 7 nm and 5 nm), but transistors aren’t getting (much) faster anymore. It’s nothing new that, if the domain is important enough (say, graphics, ML, or even networking), then specialized hardware will do better, however it’s almost always more cost effective to organize this as an accelerator to an existing traditional CPU.

RISC-V could be the “traditional CPU” and/or be an ISA inside the accelerator.