# Developing on Freedom E300 ARTY FPGA Devkit

**URL:** <https://forums.sifive.com/t/developing-on-freedom-e300-arty-fpga-devkit/1800>\
**Category:** Freedom E300\
**Created:** [November 20, 2018, 8:52pm UTC](https://forums.sifive.com/t/developing-on-freedom-e300-arty-fpga-devkit/1800 "2018-11-20T20:52:50Z")\
**Posts on this page:** 1\
**Page:** 1

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**Author:** ![Giuseppe](https://sea2.discourse-cdn.com/flex020/user_avatar/forums.sifive.com/giuseppe/32/125_2.png) [@Giuseppe](https://forums.sifive.com/u/Giuseppe)\
**Post date:** [November 20, 2018, 8:52pm UTC](https://forums.sifive.com/t/developing-on-freedom-e300-arty-fpga-devkit/1800/1 "2018-11-20T20:52:51Z")

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I have a Freedom E300 ARTY FPGA Devkit. I am able to generate my own bitstream and run the examples from Freedom E SDK.

Few questions.

Right now, I am modifying the Chisel implementation of the core (Rocket Chip generator). For example, I am editing the Scala files in `rocket-chip/src/main/scala/rocket/` ([https://github.com/sifive/freedom](https://github.com/sifive/freedom)).

When I regenerate the Verilog files,  
`make -f Makefile.e300artydevkit clean verilog`  
it generates a single 23MB file: `builds/e300artydevkit/sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.v`.

**Q1.** Is it possible to generate multiple Verilog files, e.g. one for the ALU, one for the decode stage, etc.? The suggested to use the `--split-modules` flag for the FIRTTL invocation, but it did not work.

**Q2.** Can I attach an ILA in Vivado to monitor the core on the FPGA?

**Q3.** Can I co-simulate software / modified hardware (no FPGA)? [Edit: I assume I can do: [https://github.com/freechipsproject/rocket-chip#emulator](https://github.com/freechipsproject/rocket-chip#emulator)]