The ISA does not specify the CPU cycles for each instruction. There are many possible ways to build a CPU that executes the RISC-V instruction set, depending on what trade-off you want in core size, power, speed, cost etc. Some such as Olof Kindgren’s award-winning “SERV” bit-serial FPGA core take several dozen clock cycles per instruction. Others such as SiFive’s superscalar 7-series and 8-series cores can execute on average more than one instruction per clock cycle.
In general, SiFive’s cores execute one instruction per clock cycle per pipeline, if a suitable instruction is available for dispatch, if required inputs are available. There can be delays if loads do not hit in cache or TIM, or if branches are mispredicted. You need to read the datasheet for the core you are interested in to get information, and even then only some cores in some specially-configured deterministic configurations produce guaranteed execution times.
RISC-V provides performance counter CSRs so that you can measure the number of instructions executed and number of clock cycles actually used by your code. SiFive cores can be configured to have additional performance monitoring counters such as cache misses, pipeline interlocks, branch mispredicts and so forth.