# Building E300 for Arty fails **URL:** \ **Category:** Freedom E300\ **Created:** [March 2, 2018, 6:43pm UTC](https://forums.sifive.com/t/building-e300-for-arty-fails/1065 "2018-03-02T18:43:43Z")\ **Posts on this page:** 6\ **Page:** 1
**Author:** ![Santi](https://avatars.discourse-cdn.com/v4/letter/s/439d5e/32.png) [@Santi](https://forums.sifive.com/u/Santi)\ **Post date:** [March 2, 2018, 6:43pm UTC](https://forums.sifive.com/t/building-e300-for-arty-fails/1065/1 "2018-03-02T18:43:43Z")
Hi, I have been trying to build the E300 for the Arty to take a peek at how it hooks up the debug interface out to the GPIO pin headers. Me and my team have tried putting the freedom platform on the Genesys Digilent board and have been having trouble getting debug capability on it. I was hoping to use the E300 verilog design to get an idea on what is the golden way of doing it. So far when I try to make the verilog for the Arty, it fails to build. The system seems to fail at compiling the fpga-shells project. Also when initializing the git submodules, it doesn’t seem to be able to clone the ucb-bar/riscv-test-env repository. Running the command: make -f Makefile.e300artydevkit verilog Produces the following output: mkdir -p /home/sgutierrez/freedom/builds/u500vc707devkit/ java -jar /home/sgutierrez/freedom/rocket-chip/sbt-launch.jar “run-main freechips.rocketchip.system.Generator /home/sgutierrez/freedom/builds/u500vc707devkit sifive.freedom.unleashed.u500vc707devkit U500VC707DevKitFPGAChip sifive.freedom.unleashed.u500vc707devkit U500VC707DevKitConfig” [info] Loading project definition from /home/sgutierrez/freedom/rocket-chip/project Using addons: [info] Set current project to freedom (in build file:/home/sgutierrez/freedom/) [info] Compiling 1 Scala source to /home/sgutierrez/freedom/rocket-chip/chisel3/target/scala-2.11/classes… [info] Packaging /home/sgutierrez/freedom/rocket-chip/chisel3/target/scala-2.11/chisel3\_2.11-3.1-SNAPSHOT.jar … [info] Done packaging. [info] Compiling 10 Scala sources to /home/sgutierrez/freedom/fpga-shells/target/scala-2.11/classes… [error] /home/sgutierrez/freedom/fpga-shells/src/main/scala/ip/xilinx/Xilinx.scala:9: object blocks is not a member of package sifive [error] import sifive.blocks.devices.pinctrl.{BasePin} [error] ^ [error] /home/sgutierrez/freedom/fpga-shells/src/main/scala/ip/xilinx/Xilinx.scala:65: not found: type BasePin [error] def apply (pin: Analog, ctrl: BasePin): Bool = { [error] ^ [error] /home/sgutierrez/freedom/fpga-shells/src/main/scala/shell/xilinx/ArtyShell.scala:11: object blocks is not a member of package sifive [error] import sifive.blocks.devices.gpio.\_ [error] ^ [error] /home/sgutierrez/freedom/fpga-shells/src/main/scala/shell/xilinx/ArtyShell.scala:12: object blocks is not a member of package sifive [error] import sifive.blocks.devices.pwm.\_ [error] ^ [error] /home/sgutierrez/freedom/fpga-shells/src/main/scala/shell/xilinx/ArtyShell.scala:13: object blocks is not a member of package sifive [error] import sifive.blocks.devices.spi.\_ [error] ^ [error] /home/sgutierrez/freedom/fpga-shells/src/main/scala/shell/xilinx/ArtyShell.scala:14: object blocks is not a member of package sifive [error] import sifive.blocks.devices.uart.\_ [error] ^ [error] /home/sgutierrez/freedom/fpga-shells/src/main/scala/shell/xilinx/ArtyShell.scala:15: object blocks is not a member of package sifive [error] import sifive.blocks.devices.pinctrl.{BasePin} [error] ^ [error] /home/sgutierrez/freedom/fpga-shells/src/main/scala/shell/xilinx/ArtyShell.scala:163: not found: type HasPeripherySPIFlashModuleImp [error] def connectSPIFlash(dut: HasPeripherySPIFlashModuleImp): Unit = { [error] ^ [error] /home/sgutierrez/freedom/fpga-shells/src/main/scala/shell/xilinx/ArtyShell.scala:164: not found: value PeripherySPIFlashKey [error] val qspiParams = p(PeripherySPIFlashKey) [error] ^ [error] /home/sgutierrez/freedom/fpga-shells/src/main/scala/shell/xilinx/ArtyShell.scala:167: not found: type SPIPins [error] val qspi\_pins = Wire(new SPIPins(() =\> {new BasePin()}, qspi\_params)) [error] ^ [error] /home/sgutierrez/freedom/fpga-shells/src/main/scala/shell/xilinx/ArtyShell.scala:167: not found: type BasePin [error] val qspi\_pins = Wire(new SPIPins(() =\> {new BasePin()}, qspi\_params)) [error] ^ [error] /home/sgutierrez/freedom/fpga-shells/src/main/scala/shell/xilinx/ArtyShell.scala:169: not found: value SPIPinsFromPort [error] SPIPinsFromPort(qspi\_pins, [error] ^ [error] /home/sgutierrez/freedom/fpga-shells/src/main/scala/shell/xilinx/ArtyShell.scala:173: not found: value syncStages [error] syncStages = qspi\_params.sampleDelay [error] ^ [error] /home/sgutierrez/freedom/fpga-shells/src/main/scala/shell/xilinx/ArtyShell.scala:239: not found: type HasPeripheryUARTModuleImp [error] def connectUART(dut: HasPeripheryUARTModuleImp): Unit = { [error] ^ [error] /home/sgutierrez/freedom/fpga-shells/src/main/scala/shell/xilinx/ArtyShell.scala:240: not found: value PeripheryUARTKey [error] val uartParams = p(PeripheryUARTKey) [error] ^ [error] /home/sgutierrez/freedom/fpga-shells/src/main/scala/shell/xilinx/VC707Shell.scala:12: object blocks is not a member of package sifive [error] import sifive.blocks.devices.gpio.\_ [error] ^ [error] /home/sgutierrez/freedom/fpga-shells/src/main/scala/shell/xilinx/VC707Shell.scala:13: object blocks is not a member of package sifive [error] import sifive.blocks.devices.spi.\_ [error] ^ [error] /home/sgutierrez/freedom/fpga-shells/src/main/scala/shell/xilinx/VC707Shell.scala:14: object blocks is not a member of package sifive [error] import sifive.blocks.devices.uart.\_ [error] ^ [error] /home/sgutierrez/freedom/fpga-shells/src/main/scala/shell/xilinx/VC707Shell.scala:246: not found: type HasPeripheryUARTModuleImp [error] def connectUART(dut: HasPeripheryUARTModuleImp): Unit = { [error] ^ [error] /home/sgutierrez/freedom/fpga-shells/src/main/scala/shell/xilinx/VC707Shell.scala:247: not found: value PeripheryUARTKey [error] val uartParams = p(PeripheryUARTKey) [error] ^ [error] /home/sgutierrez/freedom/fpga-shells/src/main/scala/shell/xilinx/VC707Shell.scala:259: not found: type HasPeripherySPIModuleImp [error] def connectSPI(dut: HasPeripherySPIModuleImp): Unit = { [error] ^ [error] 21 errors found [error] (fpgaShells/compile:compileIncremental) Compilation failed [error] Total time: 10 s, completed Mar 2, 2018 10:21:42 AM [common.mk:48](http://common.mk:48): recipe for target ‘/home/sgutierrez/freedom/builds/u500vc707devkit/sifive.freedom.unleashed.u500vc707devkit.U500VC707DevKitConfig.fir’ failed make: \*\*\* [/home/sgutierrez/freedom/builds/u500vc707devkit/sifive.freedom.unleashed.u500vc707devkit.U500VC707DevKitConfig.fir] Error 1 Any help would be great. Thank you. ---
**Author:** ![mwachs5](https://sea2.discourse-cdn.com/flex020/user_avatar/forums.sifive.com/mwachs5/32/13_2.png) [@mwachs5](https://forums.sifive.com/u/mwachs5)\ **Post date:** [March 2, 2018, 7:33pm UTC](https://forums.sifive.com/t/building-e300-for-arty-fails/1065/2 "2018-03-02T19:33:39Z")
The errors make it look like you don’t have all the necessary submodules. Are you sure that you updated all your submodules? So, when you cloned the repository, did you do: ```auto git clone https://github.com/sifive/freedom cd freedom git submodule update --init --recursive ``` ---
**Author:** ![Santi](https://avatars.discourse-cdn.com/v4/letter/s/439d5e/32.png) [@Santi](https://forums.sifive.com/u/Santi)\ **Post date:** [March 2, 2018, 9:00pm UTC](https://forums.sifive.com/t/building-e300-for-arty-fails/1065/3 "2018-03-02T21:00:06Z")
Yup. I cloned the Repo, cd into it, then ran the same git submodule call you did. Like I said however, that didn’t completely finish either. This is the error I get when doing that again. ``` Cloning into 'env'... fatal: unable to connect to github.com: github.com[0: 192.30.253.113]: errno=Connection refused github.com[1: 192.30.253.112]: errno=Connection refused fatal: clone of 'git://github.com/ucb-bar/riscv-test-env.git' into submodule path 'env' failed Failed to recurse into submodule path 'rocket-chip/torture' Failed to recurse into submodule path 'rocket-chip' ``` I looked into why it might be failing and it looks like the URL for the clone is incorrect. The same repo has been moved to [github.com/riscv/riscv-test-env](http://github.com/riscv/riscv-test-env) but the submodule reference snapshot has the old URL. ---
**Author:** ![rxia](https://avatars.discourse-cdn.com/v4/letter/r/c67d28/32.png) [@rxia](https://forums.sifive.com/u/rxia)\ **Post date:** [March 2, 2018, 9:38pm UTC](https://forums.sifive.com/t/building-e300-for-arty-fails/1065/4 "2018-03-02T21:38:21Z")
The submodule failed to check out because it is configured to use the `git://` protocol, which requires that you have your SSH added to a GitHub account. The submodule in question has been corrected to use the `http://` protocol, but you might be on an older branch that still uses the `git://` protocol. You can manually change this in your local git repository by editing the following file in the `.git/` directory: ``` .git/modules/rocket-chip/modules/riscv-tools/modules/riscv-tests/config ``` And under the `[submodule "env"]` section, changing the value of `url` to `https://github.com/riscv/riscv-test-env.git` After making those changes, you can try running `git submodule update --init --recursive` again. ---
**Author:** ![Santi](https://avatars.discourse-cdn.com/v4/letter/s/439d5e/32.png) [@Santi](https://forums.sifive.com/u/Santi)\ **Post date:** [March 5, 2018, 6:05pm UTC](https://forums.sifive.com/t/building-e300-for-arty-fails/1065/5 "2018-03-05T18:05:13Z")
Thank You! Managed to get it to build. ---
**Author:** ![martintian](https://avatars.discourse-cdn.com/v4/letter/m/e56c9b/32.png) [@martintian](https://forums.sifive.com/u/martintian)\ **Post date:** [October 16, 2018, 11:08am UTC](https://forums.sifive.com/t/building-e300-for-arty-fails/1065/6 "2018-10-16T11:08:00Z")
hi Santi， are you try it again, and it’s ok now ?