# Barrel shifter

**URL:** <https://forums.sifive.com/t/barrel-shifter/1279>\
**Category:** RISC-V\
**Created:** [June 5, 2018, 2:25pm UTC](https://forums.sifive.com/t/barrel-shifter/1279 "2018-06-05T14:25:25Z")\
**Posts on this page:** 7\
**Page:** 1

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**Author:** ![ddlawrence](https://avatars.discourse-cdn.com/v4/letter/d/57b2e6/32.png) [@ddlawrence](https://forums.sifive.com/u/ddlawrence)\
**Post date:** [June 5, 2018, 2:25pm UTC](https://forums.sifive.com/t/barrel-shifter/1279/1 "2018-06-05T14:25:25Z")

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Hi. Does RISC-V incorporate a barrel shifter?  
I did not see it in the riscv\_specv2.2.

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**Author:** ![bruce](https://sea2.discourse-cdn.com/flex020/user_avatar/forums.sifive.com/bruce/32/452_2.png) [@bruce](https://forums.sifive.com/u/bruce)\
**Post date:** [June 5, 2018, 2:59pm UTC](https://forums.sifive.com/t/barrel-shifter/1279/2 "2018-06-05T14:59:29Z")

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The RISC-V base integer ISA has instructions to shift a register left or right by a number of bit positions specified by a literal in the instruction or by the contents of a register.

I don’t think any constraint is placed on the implementation of shifts. A conforming implementation could shift by one bit per clock cycle until the specified shift amount had been achieved.

In practice, I’m not aware of any RISC-V implementations without fast (single-cycle) shifts by arbitrary amounts. Certainly not any current SiFive processor.

And compilers assume they can quickly sign-extend or zero-extend a value with a left shift followed by an arithmetic or logical right shift.

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**Author:** ![ddlawrence](https://avatars.discourse-cdn.com/v4/letter/d/57b2e6/32.png) [@ddlawrence](https://forums.sifive.com/u/ddlawrence)\
**Post date:** [June 6, 2018, 6:31am UTC](https://forums.sifive.com/t/barrel-shifter/1279/3 "2018-06-06T06:31:45Z")

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Hi, you said:

> [@bruce](#):
>
> In practice, I’m not aware of any RISC-V implementations without fast (single-cycle) shifts by arbitrary amounts.

Is this statement correct? It looks like a double negative.  
SLLI/SRLI looks like it will do the shifting you describe.  
Actually I need very fast rotation for encryption.  
thanks…dd

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**Author:** ![bruce](https://sea2.discourse-cdn.com/flex020/user_avatar/forums.sifive.com/bruce/32/452_2.png) [@bruce](https://forums.sifive.com/u/bruce)\
**Post date:** [June 6, 2018, 7:55am UTC](https://forums.sifive.com/t/barrel-shifter/1279/4 "2018-06-06T07:55:09Z")

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Yes, it is correct. All RISC-V implementations I’m aware of have fast shifters.

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**Author:** ![Humanoid](https://avatars.discourse-cdn.com/v4/letter/h/6de8d8/32.png) [@Humanoid](https://forums.sifive.com/u/Humanoid)\
**Post date:** [June 6, 2018, 10:53am UTC](https://forums.sifive.com/t/barrel-shifter/1279/5 "2018-06-06T10:53:27Z")

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Rotations will be available in the future “B extension”. I don’t believe the E310 or U540 support the B extension. So you’ll have to use SLL and SRL, and then OR the results together.

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**Author:** ![jsburke](https://avatars.discourse-cdn.com/v4/letter/j/e95f7d/32.png) [@jsburke](https://forums.sifive.com/u/jsburke)\
**Post date:** [June 6, 2018, 7:58pm UTC](https://forums.sifive.com/t/barrel-shifter/1279/6 "2018-06-06T19:58:24Z")

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BlueSpec has one with the option of serial shifts :

[Serial shift on their github](https://github.com/bluespec/Piccolo/blob/master/src_Core/Core/Shifter_Box.bsv)

However, the make files default to shifters that finish in a single cycle:

[Make defining barrel shift](https://github.com/bluespec/Piccolo/blob/b74ca5c77e75cc942e00ebba12c36d3d3719f0a1/sim_Bluesim/Makefile#L44)

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**Author:** ![ddlawrence](https://avatars.discourse-cdn.com/v4/letter/d/57b2e6/32.png) [@ddlawrence](https://forums.sifive.com/u/ddlawrence)\
**Post date:** [June 7, 2018, 5:41am UTC](https://forums.sifive.com/t/barrel-shifter/1279/7 "2018-06-07T05:41:05Z")

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ok thx
