I did some more research into this. Reading the sifive-blocks code I came across this commit:
It looks like writes to the txdata register with the txfull bit set will quash the sending of the byte (effectively making it so that write is ignored by the device).
(At least that’s my assumption, I don’t really know the language that the blocks are written in, and I’m not a hardware guy).
I have to assume that the atomics working on IO registers are not atomic with respect to operations within the device (such as consuming bytes from the FIFO), but I assume they are atomic with respect to other bus masters writing to the registers.
I think in this case it means that the documentation is incorrect and should be updated to make it clear that an amoor instruction is required and that writing to the txdata register with txfull bit set will result in the write being ignored by the device.
Is this accurate? Is the documentation source available? If so, I’ll write a patch.