# A problem about Debug Module

**URL:** <https://forums.sifive.com/t/a-problem-about-debug-module/746>\
**Category:** RISC-V\
**Created:** [September 7, 2017, 10:48am UTC](https://forums.sifive.com/t/a-problem-about-debug-module/746 "2017-09-07T10:48:24Z")\
**Posts on this page:** 4\
**Page:** 1

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**Author:** ![huangwanneng](https://avatars.discourse-cdn.com/v4/letter/h/4af34b/32.png) [@huangwanneng](https://forums.sifive.com/u/huangwanneng)\
**Post date:** [September 7, 2017, 10:48am UTC](https://forums.sifive.com/t/a-problem-about-debug-module/746/1 "2017-09-07T10:48:24Z")

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Hi,all  
When I read a word from memory using program buffer,I find that a error was returned back in **cmderr** abstractcs.The cmderr is 4,The detailed information is that “An abstract command couldn’t execute because the hart wasn’t in the expected state (running/halted).”  
I don’t know how to solve the problem.Whether I nedd to set the **hartsel** and **haltreq**?

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**Author:** ![mwachs5](https://sea2.discourse-cdn.com/flex020/user_avatar/forums.sifive.com/mwachs5/32/13_2.png) [@mwachs5](https://forums.sifive.com/u/mwachs5)\
**Post date:** [September 7, 2017, 3:01pm UTC](https://forums.sifive.com/t/a-problem-about-debug-module/746/2 "2017-09-07T15:01:57Z")

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Yes, the SiFive implementation of the debug spec requires that the core be _halted_ before attempting to execute abstract commands.

> When a debugger wants to halt a single hart it selects it in `hartsel` and sets `haltreq`, then waits  
> for `allhalted` to indicate the hart is halted before clearing `haltreq` to 0.

If you do that before you try to read the word from memory with the program buffer, it should work.

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<div class="post-metadata">

**Author:** ![huangwanneng](https://avatars.discourse-cdn.com/v4/letter/h/4af34b/32.png) [@huangwanneng](https://forums.sifive.com/u/huangwanneng)\
**Post date:** [September 8, 2017, 10:23am UTC](https://forums.sifive.com/t/a-problem-about-debug-module/746/3 "2017-09-08T10:23:39Z")

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Thanks,however I find that I failed to set the **haltreq** to 1, but I can success to set dmactive to [1.So](http://1.So) I don’t know what problem happened.  
And I also don’t know how to set **hartsel** because I don’t know whether **a single hart** or **multiple harts** are running after being reset at power-up.If it is a single hart,what is the index of the hart to select.  
I just want to halt all the hart in order to using Astract command.  
_Additional information_：Hart Summary is 0x0000\_0000;Hart Info is 0x0011\_1380.

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<div class="post-metadata">

**Author:** ![mwachs5](https://sea2.discourse-cdn.com/flex020/user_avatar/forums.sifive.com/mwachs5/32/13_2.png) [@mwachs5](https://forums.sifive.com/u/mwachs5)\
**Post date:** [September 8, 2017, 5:55pm UTC](https://forums.sifive.com/t/a-problem-about-debug-module/746/4 "2017-09-08T17:55:43Z")

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I don’t believe that `haltreq` is readable in all implementations, so it’s OK that you can’t read it back. But yes, you will need to set `dmactive` to 1 in order to do anything in the Debug Module.

You can figure out how many harts there are by writing to hartsel, then reading `dmstatus` to see if `anynonexistent` or `allrunning`. If you set hartsel to too high a number, then you would get `anynonexistent` status.

In general for a single core system it’s most likely you just want to set hartsel to 0.

Once you have successfully halted the hart, you can know by checking `dmstatus` to see `allhalted`.