# General **URL:** https://forums.sifive.com/c/archive/general/7.md [Latest](https://forums.sifive.com/latest.md) · [Categories](https://forums.sifive.com/categories.md) --- ## [About the General category](https://forums.sifive.com/t/about-the-general-category/19)
**Author:** [@phil.dworsky](https://forums.sifive.com/u/phil.dworsky)\ **Replies:** 0\ **Last updated:** [November 16, 2020, 8:00am UTC](https://forums.sifive.com/t/about-the-general-category/19 "2020-11-16T08:00:00Z")
\*\*\* NOTICE: SiFive Forums are evolving \*\*\* NOTE: THIS FORUM HAS BEEN MADE READ-ONLY as of Nov 16, 2020. General Topics for Discussion Thank you for participating in the RISC-V community and for making RISC-V and SiFiv… --- ## [SiFive Forums are Evolving - some will be made read-only by Nov. 15, 2020](https://forums.sifive.com/t/sifive-forums-are-evolving-some-will-be-made-read-only-by-nov-15-2020/4196)
**Author:** [@phil.dworsky](https://forums.sifive.com/u/phil.dworsky)\ **Replies:** 0\ **Last updated:** [November 11, 2020, 9:49pm UTC](https://forums.sifive.com/t/sifive-forums-are-evolving-some-will-be-made-read-only-by-nov-15-2020/4196 "2020-11-11T21:49:44Z")
\*\*\* NOTICE: SiFive Forums are evolving \*\*\* Thank you for participating in the RISC-V community and for making RISC-V and SiFive so successful, so far! Some of the SiFive Forum Categories have been made READ-ONLY as of… --- ## [THIS "General" FORUM CATEGORY WILL BE READ-ONLY after Nov 15, 2020](https://forums.sifive.com/t/this-general-forum-category-will-be-read-only-after-nov-15-2020/4194)
**Author:** [@phil.dworsky](https://forums.sifive.com/u/phil.dworsky)\ **Replies:** 0\ **Last updated:** [November 11, 2020, 9:37pm UTC](https://forums.sifive.com/t/this-general-forum-category-will-be-read-only-after-nov-15-2020/4194 "2020-11-11T21:37:48Z")
\*\*\* NOTICE: SiFive Forums are evolving \*\*\* NOTE: THIS FORUM WILL BE MADE READ-ONLY Nov 15, 2020. General Topics for Discussion Thank you for participating in the RISC-V community and for making RISC-V and SiFive so su… --- ## [SiFive E24 core clock frequency in Dev Kit Arty7](https://forums.sifive.com/t/sifive-e24-core-clock-frequency-in-dev-kit-arty7/4170)
**Author:** [@EttoreGili](https://forums.sifive.com/u/EttoreGili)\ **Replies:** 0\ **Last updated:** [November 4, 2020, 1:39pm UTC](https://forums.sifive.com/t/sifive-e24-core-clock-frequency-in-dev-kit-arty7/4170 "2020-11-04T13:39:24Z")
Hi, I am using an Arty7 (incorporating the FPGA Xilinx Artix A100T), as suggested in the official document “SiFive Core IP Arty FPGA Eval Kit User Guide”, to test the E24 core (beacuse my company is evaluating to buy its… --- ## [Welcome to SiFive Forums - they are evolving!](https://forums.sifive.com/t/welcome-to-sifive-forums-they-are-evolving/25)
**Author:** [@jackckang](https://forums.sifive.com/u/jackckang)\ **Replies:** 4\ **Last updated:** [October 29, 2020, 6:08pm UTC](https://forums.sifive.com/t/welcome-to-sifive-forums-they-are-evolving/25 "2020-10-29T18:08:45Z")
\*\*\* NOTICE: SiFive Forums are evolving \*\*\* Thank you for participating in the RISC-V community and for making RISC-V and SiFive so successful, so far! We originally conceived the SiFive Forums as the meeting place for… --- ## [Failure to import standalone project into Freedom Studio](https://forums.sifive.com/t/failure-to-import-standalone-project-into-freedom-studio/4129)
**Author:** [@twpedersen](https://forums.sifive.com/u/twpedersen)\ **Replies:** 5\ **Last updated:** [October 28, 2020, 6:24pm UTC](https://forums.sifive.com/t/failure-to-import-standalone-project-into-freedom-studio/4129 "2020-10-28T18:24:34Z")
Hello, I’m trying to build and debug a standalone project from within Freedom Studio (4.7.2.2020-06-3). I’m not sure if the following should work, but here are the steps: create a standalone project from freedom-e-sd… --- ## [Freedom E SDK FreeRTOS blinky demo issue](https://forums.sifive.com/t/freedom-e-sdk-freertos-blinky-demo-issue/4118)
**Author:** [@rluna319](https://forums.sifive.com/u/rluna319)\ **Replies:** 3\ **Last updated:** [October 28, 2020, 4:52pm UTC](https://forums.sifive.com/t/freedom-e-sdk-freertos-blinky-demo-issue/4118 "2020-10-28T16:52:31Z")
Hi, I am encountering a problem when debugging the qemu\_sifive\_e31\_example\_freertos\_blinky demo project from the Freedom E SDK. I get Invalid register read/write errors printed to the console window. I am not sure how … --- ## [Deployment and Installation Software with RISC-V compatibility](https://forums.sifive.com/t/deployment-and-installation-software-with-risc-v-compatibility/4138)
**Author:** [@surendrallam](https://forums.sifive.com/u/surendrallam)\ **Replies:** 3\ **Last updated:** [October 28, 2020, 4:44pm UTC](https://forums.sifive.com/t/deployment-and-installation-software-with-risc-v-compatibility/4138 "2020-10-28T16:44:09Z")
Hello, Surendra here, I was searching for System Deployment and Installation solution, but couldn't find any, which are RISC-V compatibility. So, please suggest a Software solution? Below are the required functio… --- ## [Why hifive board has swd debug port?](https://forums.sifive.com/t/why-hifive-board-has-swd-debug-port/4062)
**Author:** [@bsvtgc](https://forums.sifive.com/u/bsvtgc)\ **Replies:** 1\ **Last updated:** [September 23, 2020, 7:04pm UTC](https://forums.sifive.com/t/why-hifive-board-has-swd-debug-port/4062 "2020-09-23T19:04:15Z")
I see the HIfive1 Rev B board schematics has support for JTAG & SWD debug port. If I am right, SWD is a ARM specific debug port, why is it in RISC-V hifive board? --- ## [Discussion: if possible to add risc-v support for android gcc toolchain](https://forums.sifive.com/t/discussion-if-possible-to-add-risc-v-support-for-android-gcc-toolchain/4056)
**Author:** [@unicornx](https://forums.sifive.com/u/unicornx)\ **Replies:** 2\ **Last updated:** [September 22, 2020, 5:38am UTC](https://forums.sifive.com/t/discussion-if-possible-to-add-risc-v-support-for-android-gcc-toolchain/4056 "2020-09-22T05:38:04Z")
hello, I am trying to port android gcc to support riscv. I see the latest android cross gcc version is 4.9. I wonder if possible to do porting work with this version, because I know current riscv-gnu-toolchain has moved… --- ## [\[Freedom Studio\] configure: error: C compiler cannot create executables](https://forums.sifive.com/t/freedom-studio-configure-error-c-compiler-cannot-create-executables/4022)
**Author:** [@TaLucGiaHoang](https://forums.sifive.com/u/TaLucGiaHoang)\ **Replies:** 2\ **Last updated:** [September 7, 2020, 3:11am UTC](https://forums.sifive.com/t/freedom-studio-configure-error-c-compiler-cannot-create-executables/4022 "2020-09-07T03:11:20Z")
I have downloaded FreedomStudio-2020-06-3-win64 package and used Create a new Freedom E SDK Software Project by SiFive tools to create a welcome-example for my HiFive1 Rev B. I got some errors when building this project.… --- ## [Is there an open source graphics card that utilises Risc-V or something different?](https://forums.sifive.com/t/is-there-an-open-source-graphics-card-that-utilises-risc-v-or-something-different/4017)
**Author:** [@unix\_man](https://forums.sifive.com/u/unix_man)\ **Replies:** 0\ **Last updated:** [September 1, 2020, 9:09am UTC](https://forums.sifive.com/t/is-there-an-open-source-graphics-card-that-utilises-risc-v-or-something-different/4017 "2020-09-01T09:09:55Z")
I want a desktop/tower graphics card that doesn’t require any binary blobs and can compete with Nvidia and AMD gaming graphics card. Is there such one available and/or is it being developed at this time? --- ## [Boot up](https://forums.sifive.com/t/boot-up/3903)
**Author:** [@vijayasree](https://forums.sifive.com/u/vijayasree)\ **Replies:** 4\ **Last updated:** [August 6, 2020, 11:10am UTC](https://forums.sifive.com/t/boot-up/3903 "2020-08-06T11:10:27Z")
Hi Expert, I want to run software for initial bootup, I have gone through Links and Makefile and ran below command make software PROGRAM=hello TARGET=design-rtl CONFIGURATION=debug Initially, I was facing this error… --- ## [What is the right way to read MISA register?](https://forums.sifive.com/t/what-is-the-right-way-to-read-misa-register/3939)
**Author:** [@bsvtgc](https://forums.sifive.com/u/bsvtgc)\ **Replies:** 10\ **Last updated:** [August 21, 2020, 5:36pm UTC](https://forums.sifive.com/t/what-is-the-right-way-to-read-misa-register/3939 "2020-08-21T17:36:49Z")
To get the base width of CPU capability from MISA register, what is the best way to read MISA register? As per privileged spec, MISA CSR length should be base width wide. Also, its MXL field holds the MXLEN. Now, ignor… --- ## [How important is MISA register?](https://forums.sifive.com/t/how-important-is-misa-register/3938)
**Author:** [@bsvtgc](https://forums.sifive.com/u/bsvtgc)\ **Replies:** 3\ **Last updated:** [August 4, 2020, 11:35pm UTC](https://forums.sifive.com/t/how-important-is-misa-register/3938 "2020-08-04T23:35:33Z")
In the due process of choosing a board to try writing some firmware on RISC-V core, browsed the HiFIve1 Rev B board. But could n’t find MISA CSR in FE310 manual. I know its an optional register to implement. But on a sta… --- ## [Can anyone help me about transfer data to system port?](https://forums.sifive.com/t/can-anyone-help-me-about-transfer-data-to-system-port/3900)
**Author:** [@trung](https://forums.sifive.com/u/trung)\ **Replies:** 0\ **Last updated:** [July 24, 2020, 9:40am UTC](https://forums.sifive.com/t/can-anyone-help-me-about-transfer-data-to-system-port/3900 "2020-07-24T09:40:25Z")
Hi all, I having an issue with the transfer data to the system port. I writing firmware for the simulator (isa=rv32imafc) but don’t know how can do full access control from Coreplex to AHB bus. Transfer data with burs… --- ## [UART1 Tx pin issue on U540](https://forums.sifive.com/t/uart1-tx-pin-issue-on-u540/3891)
**Author:** [@Ashok](https://forums.sifive.com/u/Ashok)\ **Replies:** 0\ **Last updated:** [July 21, 2020, 4:41am UTC](https://forums.sifive.com/t/uart1-tx-pin-issue-on-u540/3891 "2020-07-21T04:41:20Z")
Hello All, I am working UART on U540 board. I am facing one issue like, from UART1 Tx pin I am not able to get any signal on CRO. If that pin gets damaged, How to fix that issue…? --- ## [Where the peripheral address and register map can be done in s21 freedom sdk package](https://forums.sifive.com/t/where-the-peripheral-address-and-register-map-can-be-done-in-s21-freedom-sdk-package/3831)
**Author:** [@ophina](https://forums.sifive.com/u/ophina)\ **Replies:** 0\ **Last updated:** [June 30, 2020, 8:47am UTC](https://forums.sifive.com/t/where-the-peripheral-address-and-register-map-can-be-done-in-s21-freedom-sdk-package/3831 "2020-06-30T08:47:33Z")
How new peripheral address can be mapped in sifive environment --- ## [Using vcs tool to simulate rocket-chip failure through jtag](https://forums.sifive.com/t/using-vcs-tool-to-simulate-rocket-chip-failure-through-jtag/3829)
**Author:** [@123456789](https://forums.sifive.com/u/123456789)\ **Replies:** 0\ **Last updated:** [June 30, 2020, 8:03am UTC](https://forums.sifive.com/t/using-vcs-tool-to-simulate-rocket-chip-failure-through-jtag/3829 "2020-06-30T08:03:14Z")
Hi, I am using vcs to simulate downloading the program from jtag. I used openocd and jtag\_vpi.v. When I tried to run openocd scripts, I got the following error. Info : only one transport option; autoselect ‘jtag’ Info… --- ## [FreedomStudio QEMU Debugging error issue](https://forums.sifive.com/t/freedomstudio-qemu-debugging-error-issue/3791)
**Author:** [@HKChoi](https://forums.sifive.com/u/HKChoi)\ **Replies:** 3\ **Last updated:** [June 25, 2020, 4:38pm UTC](https://forums.sifive.com/t/freedomstudio-qemu-debugging-error-issue/3791 "2020-06-25T16:38:04Z")
Hi I tried to run QEMU Debugging on IDE. But Debugger gave me an unknown error Please save me from this issue. Thanks --- ## [Problems importing files into Freedom Studio project](https://forums.sifive.com/t/problems-importing-files-into-freedom-studio-project/3749)
**Author:** [@GarethN](https://forums.sifive.com/u/GarethN)\ **Replies:** 1\ **Last updated:** [June 23, 2020, 6:55am UTC](https://forums.sifive.com/t/problems-importing-files-into-freedom-studio-project/3749 "2020-06-23T06:55:55Z")
I am attempting to use a Freedom Studio (under windows) / Arty A7 board combination to perform some performance profiling on an existing software package and am encountering a couple of problems. I have taken the basic s… --- ## [Freedom Studio on Ubuntu 18.04 launch problem](https://forums.sifive.com/t/freedom-studio-on-ubuntu-18-04-launch-problem/3548)
**Author:** [@bwooster0](https://forums.sifive.com/u/bwooster0)\ **Replies:** 5\ **Last updated:** [June 16, 2020, 5:51pm UTC](https://forums.sifive.com/t/freedom-studio-on-ubuntu-18-04-launch-problem/3548 "2020-06-16T17:51:43Z")
When I launch Freedom Studio a dialog box pops up that says: ‘Initialize SDKs’ has encountered a problem. An internal error occurred during: 'Intialize SDKs". when I click on the Details button it says: An internal e… --- ## [Running or Setting up JLink debugger freezes FreedomStudio](https://forums.sifive.com/t/running-or-setting-up-jlink-debugger-freezes-freedomstudio/3686)
**Author:** [@ARWells1](https://forums.sifive.com/u/ARWells1)\ **Replies:** 3\ **Last updated:** [May 26, 2020, 9:05pm UTC](https://forums.sifive.com/t/running-or-setting-up-jlink-debugger-freezes-freedomstudio/3686 "2020-05-26T21:05:08Z")
I installed FreedomStudio on my WIN7 machine using all the available help including the long directory name instructions. I loaded the ‘Hello’ project and had no trouble compiling and producing a HEX file. I was also abl… --- ## [Connecting to J-link Failed](https://forums.sifive.com/t/connecting-to-j-link-failed/3588)
**Author:** [@Jonas](https://forums.sifive.com/u/Jonas)\ **Replies:** 2\ **Last updated:** [May 6, 2020, 6:15am UTC](https://forums.sifive.com/t/connecting-to-j-link-failed/3588 "2020-05-06T06:15:47Z")
--- ## [Can anyone help me with how to use QEMU for RTL validation?](https://forums.sifive.com/t/can-anyone-help-me-with-how-to-use-qemu-for-rtl-validation/3563)
**Author:** [@tejasu](https://forums.sifive.com/u/tejasu)\ **Replies:** 2\ **Last updated:** [May 4, 2020, 6:36am UTC](https://forums.sifive.com/t/can-anyone-help-me-with-how-to-use-qemu-for-rtl-validation/3563 "2020-05-04T06:36:32Z")
I am looking for emulation tool which can be used to validate UART RTL IP using embedded software. Can we use QEMU emulation? If yes can anyone provide training or setup guide for QEMU emulation? --- ## [Issue with SDK and targets](https://forums.sifive.com/t/issue-with-sdk-and-targets/3577)
**Author:** [@Jonas](https://forums.sifive.com/u/Jonas)\ **Replies:** 4\ **Last updated:** [April 23, 2020, 4:38am UTC](https://forums.sifive.com/t/issue-with-sdk-and-targets/3577 "2020-04-23T04:38:06Z")
Whenever I open Freedom Studio, I always get a pop up saying An internal error occurred during: “Initialize SDKs”. bad input for FESDKOptions(). When I try to select targets for an SDK project, none are available to clic… --- ## [Virgo](https://forums.sifive.com/t/virgo/3406)
**Author:** [@jacob](https://forums.sifive.com/u/jacob)\ **Replies:** 5\ **Last updated:** [April 21, 2020, 3:56pm UTC](https://forums.sifive.com/t/virgo/3406 "2020-04-21T15:56:43Z")
Hi, I’m Jacob Gadikian from virgo.org We are working on open hardware, with the eventual “holy Grail” goal of an open source computing ecosystem, including an open source mobile phone. We want it to be easy for our use… --- ## [Is CLIC (Core Local interrupt Controller) RISC-V Compliant?](https://forums.sifive.com/t/is-clic-core-local-interrupt-controller-risc-v-compliant/3493)
**Author:** [@abet](https://forums.sifive.com/u/abet)\ **Replies:** 2\ **Last updated:** [March 24, 2020, 5:18pm UTC](https://forums.sifive.com/t/is-clic-core-local-interrupt-controller-risc-v-compliant/3493 "2020-03-24T17:18:10Z")
Hi to you all, I’m working to upgrade the CV32E40P core interrupt system. I already implemented a CLINT (core local interrupter) and I’m now considering CLIC. Looking at SiFive documentation SiFive Interrupt Cookbook, … --- ## [Why are some topic titles gray?](https://forums.sifive.com/t/why-are-some-topic-titles-gray/3471)
**Author:** [@johnsondavies](https://forums.sifive.com/u/johnsondavies)\ **Replies:** 2\ **Last updated:** [March 21, 2020, 3:35pm UTC](https://forums.sifive.com/t/why-are-some-topic-titles-gray/3471 "2020-03-21T15:35:00Z")
What’s the significance of the fact that some topic titles in this forum are gray rather than black? For example: I can’t find any explanation of this. --- ## [Freedom Studio Demo Add Files?](https://forums.sifive.com/t/freedom-studio-demo-add-files/3310)
**Author:** [@brandonbutler-dw](https://forums.sifive.com/u/brandonbutler-dw)\ **Replies:** 6\ **Last updated:** [March 19, 2020, 2:22pm UTC](https://forums.sifive.com/t/freedom-studio-demo-add-files/3310 "2020-03-19T14:22:41Z")
I am attempting to create a RV64 port of FreeRTOS. I have created a new project in Freedom Studio using the Freedom E SDk Wizard. I chose qemu-sifive-u54 as my target. I can see that there is a src folder with a make fi… [Next page](https://forums.sifive.com/c/archive/general/7.md?page=1)