# SiFive Core Designer

**URL:** https://forums.sifive.com/c/archive/core-designer/13.md

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## [About the SiFive Core Designer category](https://forums.sifive.com/t/about-the-sifive-core-designer-category/3365)

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**Author:** [@phil.dworsky](https://forums.sifive.com/u/phil.dworsky)\
**Replies:** 0\
**Last updated:** [February 19, 2020, 11:13pm UTC](https://forums.sifive.com/t/about-the-sifive-core-designer-category/3365 "2020-02-19T23:13:23Z")

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\*\*\* NOTICE: SiFive Forums are evolving \*\*\* For discussion, feedback, and suggestions regarding SiFive Core Designer - THIS FORUM HAS BEEN MADE READ-ONLY AS OF Nov 16, 2020. Thank you for participating in the RISC-V co…

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## [Freedom E300 RTL Synthesis in Artix-7 AC701](https://forums.sifive.com/t/freedom-e300-rtl-synthesis-in-artix-7-ac701/4082)

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**Author:** [@Tonmoy](https://forums.sifive.com/u/Tonmoy)\
**Replies:** 0\
**Last updated:** [October 2, 2020, 11:32am UTC](https://forums.sifive.com/t/freedom-e300-rtl-synthesis-in-artix-7-ac701/4082 "2020-10-02T11:32:42Z")

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Hello, I am a student . I have generated the SiFive Freedom E300 RTL Verilog code with Ubuntu and copy the source code to Centos 7, where my Vivado is installed. But when I generate the bitstream with Vivado and program…