# Archive **URL:** https://forums.sifive.com/c/archive/15.md [Latest](https://forums.sifive.com/latest.md) · [Categories](https://forums.sifive.com/categories.md) --- ## [About the Archive category](https://forums.sifive.com/t/about-the-archive-category/4141)
**Author:** [@phil.dworsky](https://forums.sifive.com/u/phil.dworsky)\ **Replies:** 0
\*\*\* THE ARCHIVE IS READ-ONLY \*\*\* This category contains SiFive Forums that have been archived. --- ## [Software Integration with Hardware](https://forums.sifive.com/t/software-integration-with-hardware/4261)
**Author:** [@Harishalgat](https://forums.sifive.com/u/Harishalgat)\ **Replies:** 0\ **Last updated:** [December 1, 2020, 9:51am UTC](https://forums.sifive.com/t/software-integration-with-hardware/4261 "2020-12-01T09:51:24Z")
Hello, I have a E series Processor, It has Debug trace, UART and JTAG at its top. I have timing clean bitstream for my design for the part FPGA part that is available with me. Now I am looking to generate elf file to Pr… --- ## [Spike execute extra instructions before reset vector](https://forums.sifive.com/t/spike-execute-extra-instructions-before-reset-vector/4220)
**Author:** [@panda1628](https://forums.sifive.com/u/panda1628)\ **Replies:** 3\ **Last updated:** [November 18, 2020, 6:34pm UTC](https://forums.sifive.com/t/spike-execute-extra-instructions-before-reset-vector/4220 "2020-11-18T18:34:01Z")
This is the trace of a RISC-V compliance test. The reset vector address is at 0xffffffff80000000 but spike starts at 0x1000 and execute a few instructions before the reset vector. I cannot find these instructions in th… --- ## [Make -f Makefile.e300artydevkit mcs fails](https://forums.sifive.com/t/make-f-makefile-e300artydevkit-mcs-fails/486)
**Author:** [@sflin](https://forums.sifive.com/u/sflin)\ **Replies:** 19\ **Last updated:** [November 12, 2020, 6:47pm UTC](https://forums.sifive.com/t/make-f-makefile-e300artydevkit-mcs-fails/486 "2020-11-12T18:47:22Z")
I'm using Ubuntu 16.04 on VMware. "make -f Makefile.e300artydevkit mcs" fails as follows; $ make -f Makefile.e300artydevkit mcs VSRC\_TOP=/home/osboxes/Work/freedom/builds/e300artydevkit/sifive.freedom.everywhere.e300… --- ## [Linux perf tool support](https://forums.sifive.com/t/linux-perf-tool-support/3926)
**Author:** [@thearni](https://forums.sifive.com/u/thearni)\ **Replies:** 2\ **Last updated:** [November 12, 2020, 4:57pm UTC](https://forums.sifive.com/t/linux-perf-tool-support/3926 "2020-11-12T16:57:48Z")
Hello, I was wondering if any of you would know about the progress regarding the support for the perf tool in RiscV. After installing the latest Linux kernel and the perf command line tool (that was on a HiFive Unleashe… --- ## [SiFive Forums are Evolving - some will be made read-only by Nov. 15, 2020](https://forums.sifive.com/t/sifive-forums-are-evolving-some-will-be-made-read-only-by-nov-15-2020/4196)
**Author:** [@phil.dworsky](https://forums.sifive.com/u/phil.dworsky)\ **Replies:** 0\ **Last updated:** [November 11, 2020, 9:49pm UTC](https://forums.sifive.com/t/sifive-forums-are-evolving-some-will-be-made-read-only-by-nov-15-2020/4196 "2020-11-11T21:49:44Z")
\*\*\* NOTICE: SiFive Forums are evolving \*\*\* Thank you for participating in the RISC-V community and for making RISC-V and SiFive so successful, so far! Some of the SiFive Forum Categories have been made READ-ONLY as of… --- ## [THIS "RISC-V" CATEGORY WILL BE MADE READ-ONLY AFTER Nov 15, 2020](https://forums.sifive.com/t/this-risc-v-category-will-be-made-read-only-after-nov-15-2020/4195)
**Author:** [@phil.dworsky](https://forums.sifive.com/u/phil.dworsky)\ **Replies:** 0\ **Last updated:** [November 11, 2020, 9:39pm UTC](https://forums.sifive.com/t/this-risc-v-category-will-be-made-read-only-after-nov-15-2020/4195 "2020-11-11T21:39:55Z")
\*\*\* NOTICE: SiFive Forums are evolving \*\*\* NOTE: THIS FORUM WILL BE MADE READ-ONLY Nov 15, 2020. Please move the discussion to https://riscv.org/technical/technical-forums Thank you for participating in the RISC-V co… --- ## [THIS "General" FORUM CATEGORY WILL BE READ-ONLY after Nov 15, 2020](https://forums.sifive.com/t/this-general-forum-category-will-be-read-only-after-nov-15-2020/4194)
**Author:** [@phil.dworsky](https://forums.sifive.com/u/phil.dworsky)\ **Replies:** 0\ **Last updated:** [November 11, 2020, 9:37pm UTC](https://forums.sifive.com/t/this-general-forum-category-will-be-read-only-after-nov-15-2020/4194 "2020-11-11T21:37:48Z")
\*\*\* NOTICE: SiFive Forums are evolving \*\*\* NOTE: THIS FORUM WILL BE MADE READ-ONLY Nov 15, 2020. General Topics for Discussion Thank you for participating in the RISC-V community and for making RISC-V and SiFive so su… --- ## [\[Synth 8-439\] module 'BootROM' not found](https://forums.sifive.com/t/synth-8-439-module-bootrom-not-found/4189)
**Author:** [@shiping](https://forums.sifive.com/u/shiping)\ **Replies:** 0\ **Last updated:** [November 10, 2020, 10:05pm UTC](https://forums.sifive.com/t/synth-8-439-module-bootrom-not-found/4189 "2020-11-10T22:05:10Z")
Hi, experts, I am trying to build arty\_a7\_100\_risc\_v image following the instruction here: Running a RISC-V Processor on the Arty A7 I am able to build riscv tool chain and passed verilog build.But I met error on last… --- ## [Bootrom.v is missing](https://forums.sifive.com/t/bootrom-v-is-missing/1557)
**Author:** [@elektronchika](https://forums.sifive.com/u/elektronchika)\ **Replies:** 9\ **Last updated:** [November 10, 2020, 7:28pm UTC](https://forums.sifive.com/t/bootrom-v-is-missing/1557 "2020-11-10T19:28:48Z")
Hi all, I’m trying to synthesize the generated verilog RTL of E300. I added all components into Vivado, except Bootrom.v. I simply cannot fine it anywhere. Is it possible to point it to me? Thank you! Kind regards, La… --- ## [LINK ERROR: relocation truncated to fit: R\_RISCV\_JAL against symbol](https://forums.sifive.com/t/link-error-relocation-truncated-to-fit-r-riscv-jal-against-symbol/4163)
**Author:** [@Remember](https://forums.sifive.com/u/Remember)\ **Replies:** 6\ **Last updated:** [November 10, 2020, 6:28am UTC](https://forums.sifive.com/t/link-error-relocation-truncated-to-fit-r-riscv-jal-against-symbol/4163 "2020-11-10T06:28:42Z")
Toolchain Version: riscv-none-embed-gcc-xpack v8.3.0-2.3, where the individual components’ versions are as follows: BINUTILS\_GIT\_BRANCH=${BINUTILS\_GIT\_BRANCH:-"sifive-binutils-2.32-cache-control-patch-xpack"} if \[… --- ## [SiFive E24 core clock frequency in Dev Kit Arty7](https://forums.sifive.com/t/sifive-e24-core-clock-frequency-in-dev-kit-arty7/4170)
**Author:** [@EttoreGili](https://forums.sifive.com/u/EttoreGili)\ **Replies:** 0\ **Last updated:** [November 4, 2020, 1:39pm UTC](https://forums.sifive.com/t/sifive-e24-core-clock-frequency-in-dev-kit-arty7/4170 "2020-11-04T13:39:24Z")
Hi, I am using an Arty7 (incorporating the FPGA Xilinx Artix A100T), as suggested in the official document “SiFive Core IP Arty FPGA Eval Kit User Guide”, to test the E24 core (beacuse my company is evaluating to buy its… --- ## [QEMU config file not found in Freedom Studio](https://forums.sifive.com/t/qemu-config-file-not-found-in-freedom-studio/4167)
**Author:** [@cbirchallroman](https://forums.sifive.com/u/cbirchallroman)\ **Replies:** 0\ **Last updated:** [November 4, 2020, 2:29am UTC](https://forums.sifive.com/t/qemu-config-file-not-found-in-freedom-studio/4167 "2020-11-04T02:29:08Z")
I receive the following error when I try to debug a program in Freedom Studio using the QEMU configuration: C:\\\[...\]\\freedomstudio\\SiFive\\riscv-qemu-4.2.0-2020.04.0\\bin\\qemu-system-riscv64.exe: -readconfig bsp\\qemu-sifi… --- ## [Running program which has custom instruction in SPIKE simulator results error](https://forums.sifive.com/t/running-program-which-has-custom-instruction-in-spike-simulator-results-error/4158)
**Author:** [@hegdemur](https://forums.sifive.com/u/hegdemur)\ **Replies:** 1\ **Last updated:** [November 2, 2020, 2:38pm UTC](https://forums.sifive.com/t/running-program-which-has-custom-instruction-in-spike-simulator-results-error/4158 "2020-11-02T14:38:07Z")
Hi, Currently i could successfully add a custom instruction to my gnu assembler and able to reproduce object file which has my new instruction “mod” which has opcode "02e787eb " . Now i also added same custom instructi… --- ## [Welcome to SiFive Forums - they are evolving!](https://forums.sifive.com/t/welcome-to-sifive-forums-they-are-evolving/25)
**Author:** [@jackckang](https://forums.sifive.com/u/jackckang)\ **Replies:** 4\ **Last updated:** [October 29, 2020, 6:08pm UTC](https://forums.sifive.com/t/welcome-to-sifive-forums-they-are-evolving/25 "2020-10-29T18:08:45Z")
\*\*\* NOTICE: SiFive Forums are evolving \*\*\* Thank you for participating in the RISC-V community and for making RISC-V and SiFive so successful, so far! We originally conceived the SiFive Forums as the meeting place for… --- ## [Failure to import standalone project into Freedom Studio](https://forums.sifive.com/t/failure-to-import-standalone-project-into-freedom-studio/4129)
**Author:** [@twpedersen](https://forums.sifive.com/u/twpedersen)\ **Replies:** 5\ **Last updated:** [October 28, 2020, 6:24pm UTC](https://forums.sifive.com/t/failure-to-import-standalone-project-into-freedom-studio/4129 "2020-10-28T18:24:34Z")
Hello, I’m trying to build and debug a standalone project from within Freedom Studio (4.7.2.2020-06-3). I’m not sure if the following should work, but here are the steps: create a standalone project from freedom-e-sd… --- ## [Freedom E SDK FreeRTOS blinky demo issue](https://forums.sifive.com/t/freedom-e-sdk-freertos-blinky-demo-issue/4118)
**Author:** [@rluna319](https://forums.sifive.com/u/rluna319)\ **Replies:** 3\ **Last updated:** [October 28, 2020, 4:52pm UTC](https://forums.sifive.com/t/freedom-e-sdk-freertos-blinky-demo-issue/4118 "2020-10-28T16:52:31Z")
Hi, I am encountering a problem when debugging the qemu\_sifive\_e31\_example\_freertos\_blinky demo project from the Freedom E SDK. I get Invalid register read/write errors printed to the console window. I am not sure how … --- ## [Deployment and Installation Software with RISC-V compatibility](https://forums.sifive.com/t/deployment-and-installation-software-with-risc-v-compatibility/4138)
**Author:** [@surendrallam](https://forums.sifive.com/u/surendrallam)\ **Replies:** 3\ **Last updated:** [October 28, 2020, 4:44pm UTC](https://forums.sifive.com/t/deployment-and-installation-software-with-risc-v-compatibility/4138 "2020-10-28T16:44:09Z")
Hello, Surendra here, I was searching for System Deployment and Installation solution, but couldn't find any, which are RISC-V compatibility. So, please suggest a Software solution? Below are the required functio… --- ## [SiFive implementation using vivado](https://forums.sifive.com/t/sifive-implementation-using-vivado/4137)
**Author:** [@pablo1997](https://forums.sifive.com/u/pablo1997)\ **Replies:** 0\ **Last updated:** [October 26, 2020, 12:23pm UTC](https://forums.sifive.com/t/sifive-implementation-using-vivado/4137 "2020-10-26T12:23:35Z")
Hi, Does anyone knows how to develope a SoC based on the rtl provided by the evaluation cores? I would like to develope it using the deisgn blocks of vivado, because I want to add some IP Cores. I have done the SoC add… --- ## [SoC FPGA SiFive E24 Implementation](https://forums.sifive.com/t/soc-fpga-sifive-e24-implementation/4123)
**Author:** [@pablo1997](https://forums.sifive.com/u/pablo1997)\ **Replies:** 1\ **Last updated:** [October 22, 2020, 6:50pm UTC](https://forums.sifive.com/t/soc-fpga-sifive-e24-implementation/4123 "2020-10-22T18:50:56Z")
Hi, I’m trying to create a basic SoC with an E24 core, an UART. I’m using to do it the block design of vivado 2019.1. I have added the E24 as a rtl module to the block design, and I have problems to connect the AHB ports… --- ## [Doubt about program FPGA with FreedomStudio](https://forums.sifive.com/t/doubt-about-program-fpga-with-freedomstudio/4124)
**Author:** [@pablo1997](https://forums.sifive.com/u/pablo1997)\ **Replies:** 1\ **Last updated:** [October 21, 2020, 4:26pm UTC](https://forums.sifive.com/t/doubt-about-program-fpga-with-freedomstudio/4124 "2020-10-21T16:26:42Z")
Hi, I have made my own SoC based in a E24 Core. There’s the option in FreedomStudio to program the FPGA using vivado, but all the manuals of FreedomStudio only talks about flashing the FPGA. I would like to know if it i… --- ## [Information on Coreplex IP Access](https://forums.sifive.com/t/information-on-coreplex-ip-access/105)
**Author:** [@dsb](https://forums.sifive.com/u/dsb)\ **Replies:** 8\ **Last updated:** [September 4, 2020, 8:54am UTC](https://forums.sifive.com/t/information-on-coreplex-ip-access/105 "2020-09-04T08:54:35Z")
Hi Sir/Madam, I have searched through the Coreplex series documentation available on dev.sifive.com I wanted to find out if Verilog of Coreplex is available for developers to prototype and build. If yes, please poin… --- ## [SoC based in· E24 Core](https://forums.sifive.com/t/soc-based-in-e24-core/4125)
**Author:** [@pablo1997](https://forums.sifive.com/u/pablo1997)\ **Replies:** 0\ **Last updated:** [October 21, 2020, 9:46am UTC](https://forums.sifive.com/t/soc-based-in-e24-core/4125 "2020-10-21T09:46:32Z")
Hi, I would like to know if it is possible to develope a basic SoC based in a SiFiveE24 with the rtl code? I would like to do it, adding it as a rtl module to a Vivado block design. Thanks --- ## [Program used for RTL Evaluation](https://forums.sifive.com/t/program-used-for-rtl-evaluation/4119)
**Author:** [@Cbugayong25](https://forums.sifive.com/u/Cbugayong25)\ **Replies:** 0\ **Last updated:** [October 20, 2020, 5:29am UTC](https://forums.sifive.com/t/program-used-for-rtl-evaluation/4119 "2020-10-20T05:29:06Z")
Good day, I’m new here with evaluating RTLs of SiFive Cores, can you reccomended me a program that’s used for Evalutating RTLs, I’ll be Evalutating U74 cores. But I can’t afford an expensive FPGA from Xilinx. Thanks --- ## [Read\_csrs/rdcycle on RV32IM](https://forums.sifive.com/t/read-csrs-rdcycle-on-rv32im/624)
**Author:** [@georg69](https://forums.sifive.com/u/georg69)\ **Replies:** 5\ **Last updated:** [October 19, 2020, 8:27pm UTC](https://forums.sifive.com/t/read-csrs-rdcycle-on-rv32im/624 "2020-10-19T20:27:18Z")
I use the RV32IM on Microsemi FPGA. rdcycle() or read\_csr(mcycle) instructions always trap. Are they supported? --- ## [Not able to debug 'hello' using freedomstudio](https://forums.sifive.com/t/not-able-to-debug-hello-using-freedomstudio/4108)
**Author:** [@b.araujo](https://forums.sifive.com/u/b.araujo)\ **Replies:** 1\ **Last updated:** [October 15, 2020, 10:23pm UTC](https://forums.sifive.com/t/not-able-to-debug-hello-using-freedomstudio/4108 "2020-10-15T22:23:51Z")
I am using freedom e300 arty devkit with a Sifive openocd on an Arduino 1.8.2. When I try to debbug the code I get these messages on the console. Open On-Chip Debugger 0.10.0+dev (SiFive OpenOCD 0.10.0-2020.04.6) Lice… --- ## [DMA available in E31 / Freedom E310 Platform](https://forums.sifive.com/t/dma-available-in-e31-freedom-e310-platform/4087)
**Author:** [@lucas-msantos](https://forums.sifive.com/u/lucas-msantos)\ **Replies:** 2\ **Last updated:** [October 15, 2020, 10:19pm UTC](https://forums.sifive.com/t/dma-available-in-e31-freedom-e310-platform/4087 "2020-10-15T22:19:12Z")
I see on the top-level diagram from Freedom E300 Platform, that its E31 core has a DMA inside it (here, Ctrl+F on top-level block diagram). When looking for it in Freedom E310 Platform, I couldn’t find any inside the E3… --- ## [How sltiu instruction compares negative value?](https://forums.sifive.com/t/how-sltiu-instruction-compares-negative-value/4109)
**Author:** [@bsvtgc](https://forums.sifive.com/u/bsvtgc)\ **Replies:** 2\ **Last updated:** [October 15, 2020, 1:56am UTC](https://forums.sifive.com/t/how-sltiu-instruction-compares-negative-value/4109 "2020-10-15T01:56:53Z")
sltiu t1, t0, -6; Will this instruction compare if t0 \< 6 (absolute value) or will it compare if t0 \< 0xfffffffa (ignoring sign) ? --- ## [User Mode Syscall](https://forums.sifive.com/t/user-mode-syscall/4106)
**Author:** [@dkhayes117](https://forums.sifive.com/u/dkhayes117)\ **Replies:** 1\ **Last updated:** [October 14, 2020, 8:27pm UTC](https://forums.sifive.com/t/user-mode-syscall/4106 "2020-10-14T20:27:58Z")
I’ve got a rough idea on how to implement a syscall for using while in user mode, but I’m not 100% sure. I plan on using a public function syscall() which will do… 1. save all of the cpu registers by pushing them ont… --- ## [Riscv-gnu-toolchain build problem while adding custom instruction](https://forums.sifive.com/t/riscv-gnu-toolchain-build-problem-while-adding-custom-instruction/4100)
**Author:** [@hegdemur](https://forums.sifive.com/u/hegdemur)\ **Replies:** 1\ **Last updated:** [October 12, 2020, 5:02pm UTC](https://forums.sifive.com/t/riscv-gnu-toolchain-build-problem-while-adding-custom-instruction/4100 "2020-10-12T17:02:46Z")
HI, I tried adding one custom instruction to existing riscv-gnu-toolchain. Below are the steps i followed. I basically want to add instruction ‘mod’(modulus) New instruction called 'mod is added to the existing riscv\_… [Next page](https://forums.sifive.com/c/archive/15.md?page=1)